+ * see Figure 8.4.1 in IMX6DQ Reference manuals:
+ * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF
+ * - BOOT ROM stack is at 0x0093FFB8
+ * - if icache/dcache is enabled (eFuse/strapping controlled) then the
+ * IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to
+ * fit between 0x00907000 and 0x00938000.
+ * - Additionally the BOOT ROM loads what they consider the firmware image
+ * which consists of a 4K header in front of us that contains the IVT, DCD
+ * and some padding thus 'our' max size is really 0x00908000 - 0x00938000
+ * or 192KB
+ */
+#define CONFIG_SPL_MAX_SIZE 0x30000
+#define CONFIG_SPL_STACK 0x0093FFB8
+/*
+ * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO 0x31000
+#else
+/*
+ * see Figure 8-3 in IMX6SDL Reference manuals: