#define CONFIG_SKIP_LOWLEVEL_INIT
/* Keep L2 Cache Disabled */
/* input clock of PLL: 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000
#define CONFIG_SKIP_LOWLEVEL_INIT
/* Keep L2 Cache Disabled */
/* input clock of PLL: 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000