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Merge branch '2019-03-25-master-imports'
[platform/kernel/u-boot.git]
/
include
/
configs
/
cyrus.h
diff --git
a/include/configs/cyrus.h
b/include/configs/cyrus.h
index
942fbe2
..
007356b
100644
(file)
--- a/
include/configs/cyrus.h
+++ b/
include/configs/cyrus.h
@@
-1,14
+1,11
@@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Based on corenet_ds.h
/*
* Based on corenet_ds.h
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_CYRUS
-
#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
#error Must call Cyrus CONFIG with a specific CPU enabled.
#endif
#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
#error Must call Cyrus CONFIG with a specific CPU enabled.
#endif
@@
-39,14
+36,9
@@
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_MP /* support multiple processors */
#define CONFIG_SYS_MMC_MAX_DEVICE 1
#define CONFIG_SYS_MMC_MAX_DEVICE 1
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff40000
-#endif
-
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
@@
-57,7
+49,6
@@
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_SDCARD)
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_SDCARD)
-#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
@@
-88,7
+79,6
@@
#undef CONFIG_POST
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#undef CONFIG_POST
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_SYS_ALT_MEMTEST
/*
* Config the L3 Cache as L3 SRAM
/*
* Config the L3 Cache as L3 SRAM
@@
-159,9
+149,6
@@
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_RAMBOOT
#endif
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-#define CONFIG_MISC_INIT_R
-
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
@@
-192,7
+179,6
@@
* open - index 2
* shorted - index 1
*/
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
@@
-316,7
+302,6
@@
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
@@
-388,7
+373,6
@@
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_TBIPA_VALUE 8
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC4"
#endif
#define CONFIG_ETHPRIME "FM1@DTSEC4"
#endif
@@
-412,7
+396,6
@@
#endif
#ifdef CONFIG_MMC
#endif
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
@@
-420,9
+403,6
@@
/*
* Miscellaneous configurable options
*/
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
@@
-490,7
+470,4
@@
#include <asm/fsl_secure_boot.h>
#include <asm/fsl_secure_boot.h>
-#ifdef CONFIG_SECURE_BOOT
-#endif
-
#endif /* __CONFIG_H */
#endif /* __CONFIG_H */