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Merge branch 'next' of git://git.denx.de/u-boot-avr32
[platform/kernel/u-boot.git]
/
include
/
configs
/
csb472.h
diff --git
a/include/configs/csb472.h
b/include/configs/csb472.h
index
316b1fe
..
d3e5ea8
100644
(file)
--- a/
include/configs/csb472.h
+++ b/
include/configs/csb472.h
@@
-33,7
+33,7
@@
* (easy to change)
*/
* (easy to change)
*/
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
+#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
@@
-73,12
+73,15
@@
#endif
/*
#endif
/*
- * BOOTP/DHCP protocol configuration
- *
+ * BOOTP options
*/
*/
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_BOOTFILESIZE )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+
/*
* Command line configuration.
/*
* Command line configuration.
@@
-178,7
+181,7
@@
*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
+#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
/* 32usec min. for LXT971A */
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
/* 32usec min. for LXT971A */
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
@@
-260,7
+263,7
@@
*
*/
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
*
*/
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
-#define C
FG_FLASH_CFI_DRIVER
1 /* use common cfi driver */
+#define C
ONFIG_FLASH_CFI_DRIVER
1 /* use common cfi driver */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
@@
-286,14
+289,6
@@
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
- * Cache configuration
- *
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32
-
-/*
* Miscellaneous board specific definitions
*
*/
* Miscellaneous board specific definitions
*
*/