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global: Migrate CONFIG_MXC_UART_BASE to CFG
[platform/kernel/u-boot.git]
/
include
/
configs
/
corvus.h
diff --git
a/include/configs/corvus.h
b/include/configs/corvus.h
index
698da6b
..
8a61086
100644
(file)
--- a/
include/configs/corvus.h
+++ b/
include/configs/corvus.h
@@
-17,35
+17,33
@@
#include <linux/sizes.h>
/*
#include <linux/sizes.h>
/*
- * Warning: changing CONFIG_
SYS_
TEXT_BASE requires
+ * Warning: changing CONFIG_TEXT_BASE requires
* adapting the initial boot program.
* Since the linker has to swallow that define, we must use a pure
* hex number here!
*/
/* ARM asynchronous clock */
* adapting the initial boot program.
* Since the linker has to swallow that define, we must use a pure
* hex number here!
*/
/* ARM asynchronous clock */
-#define C
ONFI
G_SYS_AT91_SLOW_CLOCK 32768
-#define C
ONFI
G_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define C
F
G_SYS_AT91_SLOW_CLOCK 32768
+#define C
F
G_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* serial console */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
/* SDRAM */
/* serial console */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
/* SDRAM */
-#define C
ONFI
G_SYS_SDRAM_BASE ATMEL_BASE_CS6
-#define C
ONFIG_SYS_SDRAM_SIZE
0x08000000
+#define C
F
G_SYS_SDRAM_BASE ATMEL_BASE_CS6
+#define C
FG_SYS_SDRAM_SIZE
0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
/* our ALE is AD21 */
-#define C
ONFIG_SYS_NAND_MASK_ALE
(1 << 21)
+#define C
FG_SYS_NAND_MASK_ALE
(1 << 21)
/* our CLE is AD22 */
/* our CLE is AD22 */
-#define C
ONFIG_SYS_NAND_MASK_CLE
(1 << 22)
-#define C
ONFIG_SYS_NAND_ENABLE_PIN
AT91_PIN_PC14
-#define C
ONFIG_SYS_NAND_READY_PIN
AT91_PIN_PC8
+#define C
FG_SYS_NAND_MASK_CLE
(1 << 22)
+#define C
FG_SYS_NAND_ENABLE_PIN
AT91_PIN_PC14
+#define C
FG_SYS_NAND_READY_PIN
AT91_PIN_PC8
#endif
/* DFU class support */
#endif
/* DFU class support */
@@
-55,20
+53,20
@@
/* Defines for SPL */
/* Defines for SPL */
-#define C
ONFIG_SYS_NAND_U_BOOT_SIZE
0x80000
-#define C
ONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS
_TEXT_BASE
-#define C
ONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS
_TEXT_BASE
+#define C
FG_SYS_NAND_U_BOOT_SIZE
0x80000
+#define C
FG_SYS_NAND_U_BOOT_START CONFIG
_TEXT_BASE
+#define C
FG_SYS_NAND_U_BOOT_DST CONFIG
_TEXT_BASE
-#define C
ONFIG_SYS_NAND_ECCSIZE
256
-#define C
ONFIG_SYS_NAND_ECCBYTES
3
-#define C
ONFIG_SYS_NAND_ECCPOS
{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define C
FG_SYS_NAND_ECCSIZE
256
+#define C
FG_SYS_NAND_ECCBYTES
3
+#define C
FG_SYS_NAND_ECCPOS
{ 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define C
ONFIG_SYS_MASTER_CLOCK
132096000
+#define C
FG_SYS_MASTER_CLOCK
132096000
#define AT91_PLL_LOCK_TIMEOUT 1000000
#define AT91_PLL_LOCK_TIMEOUT 1000000
-#define C
ONFIG_SYS_AT91_PLLA
0x20c73f03
-#define C
ONFIG_SYS_MCKR
0x1301
-#define C
ONFIG_SYS_MCKR_CSS
0x1302
+#define C
FG_SYS_AT91_PLLA
0x20c73f03
+#define C
FG_SYS_MCKR
0x1301
+#define C
FG_SYS_MCKR_CSS
0x1302
#endif
#endif