#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_DA850_LOWLEVEL
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_DA850_LOWLEVEL
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_HW_WATCHDOG
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_HW_WATCHDOG
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
#define CONFIG_LOADADDR 0xc0700000
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
#define CONFIG_LOADADDR 0xc0700000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS ""
#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS ""
#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
#define CONFIG_RESET_TO_RETRY
#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
#define CONFIG_RESET_TO_RETRY