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Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
[platform/kernel/u-boot.git]
/
include
/
configs
/
atstk1002.h
diff --git
a/include/configs/atstk1002.h
b/include/configs/atstk1002.h
index
e1d8f74
..
3a7d273
100644
(file)
--- a/
include/configs/atstk1002.h
+++ b/
include/configs/atstk1002.h
@@
-24,6
+24,8
@@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/arch/memory-map.h>
+
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7000 1
#define CONFIG_AVR32 1
#define CONFIG_AT32AP 1
#define CONFIG_AT32AP7000 1
@@
-39,8
+41,10
@@
#define CFG_HZ 1000
/*
#define CFG_HZ 1000
/*
- * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
- * frequency and the peripherals to run at 1/4 the PLL frequency.
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
*/
#define CONFIG_PLL 1
#define CFG_POWER_MANAGER 1
*/
#define CONFIG_PLL 1
#define CFG_POWER_MANAGER 1
@@
-48,9
+52,25
@@
#define CFG_PLL0_DIV 1
#define CFG_PLL0_MUL 7
#define CFG_PLL0_SUPPRESS_CYCLES 16
#define CFG_PLL0_DIV 1
#define CFG_PLL0_MUL 7
#define CFG_PLL0_SUPPRESS_CYCLES 16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
+ */
#define CFG_CLKDIV_CPU 0
#define CFG_CLKDIV_CPU 0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
+ */
#define CFG_CLKDIV_HSB 1
#define CFG_CLKDIV_HSB 1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
+ */
#define CFG_CLKDIV_PBA 2
#define CFG_CLKDIV_PBA 2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
+ */
#define CFG_CLKDIV_PBB 1
/*
#define CFG_CLKDIV_PBB 1
/*
@@
-78,7
+98,7
@@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
- "console=ttyS0 root=/dev/m
tdblock1 rootfstype=jffs2 fbmem=600k
"
+ "console=ttyS0 root=/dev/m
mcblk0p1 fbmem=600k rootwait=1
"
#define CONFIG_BOOTCOMMAND \
"fsload; bootm $(fileaddr)"
#define CONFIG_BOOTCOMMAND \
"fsload; bootm $(fileaddr)"
@@
-87,24
+107,19
@@
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
* data on the serial line may interrupt the boot sequence.
*/
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
* data on the serial line may interrupt the boot sequence.
*/
-#define CONFIG_BOOTDELAY
2
+#define CONFIG_BOOTDELAY
1
#define CONFIG_AUTOBOOT 1
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT 1
#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT
\
- "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Press SPACE to abort autoboot in %d seconds\n"
, bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
- * These are "locally administered ethernet addresses" generated by
- * ./tools/gen_eth_addr
- *
- * After booting the board for the first time, new addresses should be
- * generated and assigned to the environment variables "ethaddr" and
- * "eth1addr".
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
*/
*/
-#define CONFIG_ETHADDR "6a:87:71:14:cd:cb"
-#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6"
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_NET_MULTI 1
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_NET_MULTI 1
@@
-126,9
+141,9
@@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
-#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
@@
-138,6
+153,7
@@
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
#define CFG_NR_PIOS 5
#define CFG_HSDRAMC 1
#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
#define CFG_DCACHE_LINESZ 32
#define CFG_ICACHE_LINESZ 32
@@
-147,7
+163,7
@@
/* External flash on STK1000 */
#if 0
#define CFG_FLASH_CFI 1
/* External flash on STK1000 */
#if 0
#define CFG_FLASH_CFI 1
-#define C
FG_FLASH_CFI_DRIVER
1
+#define C
ONFIG_FLASH_CFI_DRIVER
1
#endif
#define CFG_FLASH_BASE 0x00000000
#endif
#define CFG_FLASH_BASE 0x00000000
@@
-157,10
+173,9
@@
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_INTRAM_BASE 0x24000000
-#define CFG_INTRAM_SIZE 0x8000
-
-#define CFG_SDRAM_BASE 0x10000000
+#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE EBI_SDRAM_BASE
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 65536
@@
-171,24
+186,19
@@
#define CFG_MALLOC_LEN (256*1024)
#define CFG_DMA_ALLOC_LEN (16384)
#define CFG_MALLOC_LEN (256*1024)
#define CFG_DMA_ALLOC_LEN (16384)
-/* Allow
2
MB for the kernel run-time image */
-#define CFG_LOAD_ADDR (
CFG_SDRAM_BASE + 0x002
00000)
+/* Allow
4
MB for the kernel run-time image */
+#define CFG_LOAD_ADDR (
EBI_SDRAM_BASE + 0x004
00000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
-#define CFG_PROMPT "U
b
oot> "
+#define CFG_PROMPT "U
-B
oot> "
#define CFG_CBSIZE 256
#define CFG_CBSIZE 256
-#define CFG_MAXARGS
8
+#define CFG_MAXARGS
16
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
-#define CFG_MEMTEST_START \
- ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
-#define CFG_MEMTEST_END \
- ({ \
- DECLARE_GLOBAL_DATA_PTR; \
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
- })
+#define CFG_MEMTEST_START EBI_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
#endif /* __CONFIG_H */
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
#endif /* __CONFIG_H */