+#ifdef CONFIG_TQM_BIGFLASH
+#define CONFIG_SYS_RIO_MEM_BASE 0xb0000000 /* base address */
+#define CONFIG_SYS_RIO_MEM_SIZE 0x10000000 /* 256M */
+#else /* !CONFIG_TQM_BIGFLASH */
+#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif /* CONFIG_TQM_BIGFLASH */
+#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#endif /* CONFIG_PCIE1 */
+
+/* NAND FLASH */
+#ifdef CONFIG_NAND
+
+#undef CONFIG_NAND_LEGACY
+
+#define CONFIG_NAND_FSL_UPM 1
+
+#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
+
+/* address distance between chip selects */
+#define CONFIG_SYS_NAND_SELECT_DEVICE 1
+#define CONFIG_SYS_NAND_CS_DIST 0x200
+
+#define CONFIG_SYS_NAND_SIZE 0x8000
+#define CONFIG_SYS_NAND0_BASE (CONFIG_SYS_CCSRBAR + 0x03010000)
+#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
+
+#if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
+#elif (CONFIG_SYS_MAX_NAND_DEVICE == 2)
+#define CONFIG_SYS_NAND_QUIET_TEST 1
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
+ CONFIG_SYS_NAND1_BASE, \
+}
+#elif (CONFIG_SYS_MAX_NAND_DEVICE == 4)
+#define CONFIG_SYS_NAND_QUIET_TEST 1
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
+ CONFIG_SYS_NAND1_BASE, \
+ CONFIG_SYS_NAND2_BASE, \
+ CONFIG_SYS_NAND3_BASE, \
+}
+#endif
+
+/* CS3 for NAND Flash */
+#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \
+ BR_MS_UPMB | BR_V)
+#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
+
+#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
+
+#endif /* CONFIG_NAND */