- * set up SIUMCR\r
- * 1 EARB 0 External arbitration\r
- * 3 EARP 000 External arbitration request priority\r
- * 4 0 0000\r
- * 1 DSHW 0 Data show cycles\r
- * 2 DBGC 00 Debug pin configuration\r
- * 2 DBPC 00 Debug port pins configuration\r
- * 1 0 0\r
- * 1 FRC 0 FRZ pin configuration\r
- * 1 DLK 0 Debug register lock\r
- * 1 OPAR 0 Odd parity\r
- * 1 PNCS 0 Parity enable for non memory controller regions\r
- * 1 DPC 0 Data parity pins configuration\r
- * 1 MPRE 0 Multiprocessor reservation enable\r
- * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)\r
- * 1 AEME 0 Async external master enable\r
- * 1 SEME 0 Sync external master enable\r
- * 1 BSC 0 Byte strobe configuration\r
- * 1 GB5E 0 GPL_B5 enable\r
- * 1 B2DD 0 Bank 2 double drive \r
- * 1 B3DD 0 Bank 3 double drive \r
- * 4 0 0000\r
+ * set up SIUMCR
+ * 1 EARB 0 External arbitration
+ * 3 EARP 000 External arbitration request priority
+ * 4 0 0000
+ * 1 DSHW 0 Data show cycles
+ * 2 DBGC 00 Debug pin configuration
+ * 2 DBPC 00 Debug port pins configuration
+ * 1 0 0
+ * 1 FRC 0 FRZ pin configuration
+ * 1 DLK 0 Debug register lock
+ * 1 OPAR 0 Odd parity
+ * 1 PNCS 0 Parity enable for non memory controller regions
+ * 1 DPC 0 Data parity pins configuration
+ * 1 MPRE 0 Multiprocessor reservation enable
+ * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
+ * 1 AEME 0 Async external master enable
+ * 1 SEME 0 Sync external master enable
+ * 1 BSC 0 Byte strobe configuration
+ * 1 GB5E 0 GPL_B5 enable
+ * 1 B2DD 0 Bank 2 double drive
+ * 1 B3DD 0 Bank 3 double drive
+ * 4 0 0000