+#ifdef CONFIG_NEW_NAND_CODE
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
+ switch((unsigned long)nandptr) { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+ break; \
+ } \
+} while(0)
+#else