+#define CONFIG_ARTOS /* include ARTOS support */
+
+/****************************************************************/
+
+#define DSP_SIZE 0x00010000 /* 64K */
+#define FPGA_SIZE 0x00010000 /* 64K */
+
+#define DSP0_BASE 0xF1000000
+#define DSP1_BASE (DSP0_BASE + DSP_SIZE)
+#define FPGA_BASE (DSP1_BASE + DSP_SIZE)
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+#define ER_SIZE 0x00010000 /* 64K */
+#define ER_BASE (FPGA_BASE + FPGA_SIZE)
+
+#define NAND_SIZE 0x00010000 /* 64K */
+#define NAND_BASE (ER_BASE + ER_SIZE)
+
+#endif
+
+/****************************************************************/
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+#define STATUS_LED_BIT 0x00000001 /* bit 31 */
+#define STATUS_LED_PERIOD (CFG_HZ / 2)
+#define STATUS_LED_STATE STATUS_LED_BLINKING
+
+#define STATUS_LED_BIT1 0x00000002 /* bit 30 */
+#define STATUS_LED_PERIOD1 (CFG_HZ / 2)
+#define STATUS_LED_STATE1 STATUS_LED_OFF
+
+#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
+#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
+#endif
+
+/*****************************************************************************/
+
+#define CFG_NAND_LEGACY
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+/* NAND */
+#define CFG_NAND_BASE NAND_BASE
+#define CONFIG_MTD_NAND_ECC_JFFS2
+
+#define CFG_MAX_NAND_DEVICE 1
+
+#define SECTORSIZE 512
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_DISABLE_CE(nand) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0040; \
+ } while(0)
+
+#define NAND_ENABLE_CE(nand) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
+ } while(0)
+
+#define NAND_CTL_CLRALE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
+ } while(0)
+
+#define NAND_CTL_SETALE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0100; \
+ } while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
+ } while(0)
+
+#define NAND_CTL_SETCLE(nandptr) \
+ do { \
+ (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0080; \
+ } while(0)
+
+#define NAND_WAIT_READY(nand) \
+ do { \
+ while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
+ ; \
+ } while (0)
+
+#define WRITE_NAND_COMMAND(d, adr) \
+ do { \
+ *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+ } while(0)
+
+#define WRITE_NAND_ADDRESS(d, adr) \
+ do { \
+ *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+ } while(0)
+
+#define WRITE_NAND(d, adr) \
+ do { \
+ *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+ } while(0)
+
+#define READ_NAND(adr) \
+ ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
+
+#endif
+
+/*****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+/* LEDs */
+
+/* last value written to the external register; we cannot read back */
+extern unsigned int last_er_val;
+
+/* led_id_t is unsigned long mask */
+typedef unsigned int led_id_t;
+
+static inline void __led_init(led_id_t mask, int state)
+{
+ unsigned int new_er_val;
+
+ if (state)
+ new_er_val = last_er_val & ~mask;
+ else
+ new_er_val = last_er_val | mask;
+
+ *(volatile unsigned int *)ER_BASE = new_er_val;
+ last_er_val = new_er_val;
+}
+
+static inline void __led_toggle(led_id_t mask)
+{
+ unsigned int new_er_val;
+
+ new_er_val = last_er_val ^ mask;
+ *(volatile unsigned int *)ER_BASE = new_er_val;
+ last_er_val = new_er_val;
+}
+
+static inline void __led_set(led_id_t mask, int state)
+{
+ unsigned int new_er_val;
+
+ if (state)
+ new_er_val = last_er_val & ~mask;
+ else
+ new_er_val = last_er_val | mask;
+
+ *(volatile unsigned int *)ER_BASE = new_er_val;
+ last_er_val = new_er_val;
+}
+
+/* MAX3100 console */
+#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_RXD_BIT 0x00000008
+
+#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_TXD_BIT 0x00000004
+
+#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_CLK_BIT 0x00000002
+
+#define MAX3100_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
+#define MAX3100_CS_BIT 0x0010
+
+#endif
+
+#endif
+
+/*************************************************************************************************/
+