#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
#define CONFIG_SYS_FLASH_BASE2 0xf8000000
#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
#define CONFIG_SYS_FLASH_BASE2 0xf8000000
#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
/*
* BAT5 128K Cacheable, non-guarded
* 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
/*
* BAT5 128K Cacheable, non-guarded
* 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_WATCHDOG /* watchdog enabled */
#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
#define CONFIG_WATCHDOG /* watchdog enabled */
#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
"bdev=sda3\0" \
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
"bdev=sda3\0" \
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \