+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
+#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH2 */
+
+#define CONFIG_UEC_ETH3 /* GETH3 */
+#define CONFIG_HAS_ETH2
+
+#ifdef CONFIG_UEC_ETH3
+#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
+#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
+#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR 2
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
+#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH3 */
+
+#define CONFIG_UEC_ETH4 /* GETH4 */
+#define CONFIG_HAS_ETH3
+
+#ifdef CONFIG_UEC_ETH4
+#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
+#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
+#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR 3
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
+#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH4 */
+
+#undef CONFIG_UEC_ETH6 /* GETH6 */
+#define CONFIG_HAS_ETH5
+
+#ifdef CONFIG_UEC_ETH6
+#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
+#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC6_PHY_ADDR 4
+#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII
+#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
+#endif /* CONFIG_UEC_ETH6 */
+
+#undef CONFIG_UEC_ETH8 /* GETH8 */
+#define CONFIG_HAS_ETH7
+
+#ifdef CONFIG_UEC_ETH8
+#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
+#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC8_PHY_ADDR 6
+#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII
+#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
+#endif /* CONFIG_UEC_ETH8 */