-#define CFG_PCIE3_MEM_BASE 0xb0000000
-#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
-#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */
-#define CFG_PCIE3_IO_BASE 0x00000000
-#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
-#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
-#define CFG_PCIE3_MEM_BASE2 0xb0200000
-#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2
-#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */