-#define CFG_DDR_SIZE 256 /* MB */
-#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
-#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
-#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */
-#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
-#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */
+#define CONFIG_SYS_DDR_SIZE 256 /* MB */
+#if defined(CONFIG_DDR_II)
+#define CONFIG_SYS_DDRCDR 0x80080001
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
+#define CONFIG_SYS_DDR_TIMING_0 0x00220802
+#define CONFIG_SYS_DDR_TIMING_1 0x38357322
+#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
+#define CONFIG_SYS_DDR_MODE 0x47d00432
+#define CONFIG_SYS_DDR_MODE2 0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
+#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#else
+#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
+#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
+#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
+#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
+#endif