-#define CFG_PCI_MEM_BASE 0x80000000
-#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
-#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CFG_PCI_MMIO_BASE 0x90000000
-#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
-#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE 0x00000000
-#define CFG_PCI_IO_PHYS 0xE0300000
-#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
-
-#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
-#define CFG_PCI_SLV_MEM_BUS 0x00000000
-#define CFG_PCI_SLV_MEM_SIZE 0x80000000
+#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE 0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000