+#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
+
+#define CONFIG_SYS_HID2 0
+
+#define CONFIG_SYS_SYPCR 0xFFFFFFC3
+#define CONFIG_SYS_BCR 0x004C0000
+#define CONFIG_SYS_SIUMCR 0x4E64C000
+#define CONFIG_SYS_SCCR 0x00000000
+
+/* local bus memory map
+ *
+ * 0x00000000-0x03FFFFFF 64MB SDRAM
+ * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
+ * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
+ * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
+ * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
+ * 0xF8000000-0xF8007FFF 32KB BCSR
+ * 0xF8100000-0xF8107FFF 32KB ATM UNI
+ * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
+ * 0xF8300000-0xF8307FFF 32KB EEPROM
+ * 0xFE000000-0xFFFFFFFF 32MB flash
+ */
+#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */
+#define CONFIG_SYS_OR0_PRELIM 0xFE000836
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */
+#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
+#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */
+#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846
+#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
+#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36
+#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
+#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
+
+#define CONFIG_SYS_RMR 0x0001
+#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR 0
+#define CONFIG_SYS_MPTPR 0x00001900
+#define CONFIG_SYS_PSRT 0x00000021
+
+/* This address must not exist */
+#define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00
+
+/* PCI Memory map (if different from default map */
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
+ PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/* PCIBR0 */
+#define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */
+#define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */
+/* PCIBR1 */
+#define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
+#define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */