+#define CONFIG_SYS_RMR RMR_CSRE
+#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR 0
+
+#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
+#undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
+
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
+#define CONFIG_SYS_OR2 0xFE002EC0
+#define CONFIG_SYS_PSDMR 0x824B36A3
+#define CONFIG_SYS_PSRT 0x13
+#define CONFIG_SYS_LSDMR 0x828737A3
+#define CONFIG_SYS_LSRT 0x13
+#define CONFIG_SYS_MPTPR 0x2800
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_SYS_OR2 0xFC002CC0
+#define CONFIG_SYS_PSDMR 0x834E24A3
+#define CONFIG_SYS_PSRT 0x13
+#define CONFIG_SYS_MPTPR 0x2800
+#else
+#define CONFIG_SYS_OR2 0xFF000CA0
+#define CONFIG_SYS_PSDMR 0x016EB452
+#define CONFIG_SYS_PSRT 0x21
+#define CONFIG_SYS_LSDMR 0x0086A522
+#define CONFIG_SYS_LSRT 0x21
+#define CONFIG_SYS_MPTPR 0x1900
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
+
+#define CONFIG_SYS_RESET_ADDRESS 0x04400000
+
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
+
+/* PCI Memory map (if different from default map */
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
+ PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
+#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
+#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */