-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
-
-#define CFG_BOOT_BASE_ADDR 0xf0000000
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */
-#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */
-#define CFG_OCM_BASE 0xe0010000 /* ocm */
-#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
-#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
-#define CFG_PCI_IOBASE 0xe8000000
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
+
+#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
+#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
+#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
+#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_PCI_IOBASE 0xe8000000