-#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
-#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
-
-#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
-#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
-#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
-#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
-
-#define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */
-#define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */
-#define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */
-#define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */
+#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
+#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */
+
+#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */
+#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
+#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
+#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */
+
+#define CONFIG_SYS_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */
+#define CONFIG_SYS_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */
+#define CONFIG_SYS_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */
+#define CONFIG_SYS_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */