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Tizen 2.0 Release
[sdk/emulator/qemu.git]
/
hw
/
etraxfs_dma.c
diff --git
a/hw/etraxfs_dma.c
b/hw/etraxfs_dma.c
index
c205ec1
..
02d0183
100644
(file)
--- a/
hw/etraxfs_dma.c
+++ b/
hw/etraxfs_dma.c
@@
-24,6
+24,7
@@
#include <stdio.h>
#include <sys/time.h>
#include "hw.h"
#include <stdio.h>
#include <sys/time.h>
#include "hw.h"
+#include "exec-memory.h"
#include "qemu-common.h"
#include "sysemu.h"
#include "qemu-common.h"
#include "sysemu.h"
@@
-185,7
+186,7
@@
struct fs_dma_channel
struct fs_dma_ctrl
{
struct fs_dma_ctrl
{
-
int map
;
+
MemoryRegion mmio
;
int nr_channels;
struct fs_dma_channel *channels;
int nr_channels;
struct fs_dma_channel *channels;
@@
-562,13
+563,17
@@
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
return 0;
}
return 0;
}
-static uint
32
_t
-dma_read
l (void *opaque, target_phys_addr_t addr
)
+static uint
64
_t
+dma_read
(void *opaque, target_phys_addr_t addr, unsigned int size
)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
uint32_t r = 0;
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
uint32_t r = 0;
+ if (size != 4) {
+ dma_rinvalid(opaque, addr);
+ }
+
/* Make addr relative to this channel and bounded to nr regs. */
c = fs_channel(addr);
addr &= 0xff;
/* Make addr relative to this channel and bounded to nr regs. */
c = fs_channel(addr);
addr &= 0xff;
@@
-599,20
+604,24
@@
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
static void
dma_update_state(struct fs_dma_ctrl *ctrl, int c)
{
static void
dma_update_state(struct fs_dma_ctrl *ctrl, int c)
{
- if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) {
- if (ctrl->channels[c].regs[RW_CFG] & 2)
- ctrl->channels[c].state = STOPPED;
- if (!(ctrl->channels[c].regs[RW_CFG] & 1))
- ctrl->channels[c].state = RST;
- }
+ if (ctrl->channels[c].regs[RW_CFG] & 2)
+ ctrl->channels[c].state = STOPPED;
+ if (!(ctrl->channels[c].regs[RW_CFG] & 1))
+ ctrl->channels[c].state = RST;
}
static void
}
static void
-dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+dma_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned int size)
{
struct fs_dma_ctrl *ctrl = opaque;
{
struct fs_dma_ctrl *ctrl = opaque;
+ uint32_t value = val64;
int c;
int c;
+ if (size != 4) {
+ dma_winvalid(opaque, addr, value);
+ }
+
/* Make addr relative to this channel and bounded to nr regs. */
c = fs_channel(addr);
addr &= 0xff;
/* Make addr relative to this channel and bounded to nr regs. */
c = fs_channel(addr);
addr &= 0xff;
@@
-668,16
+677,14
@@
dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
}
}
-static CPUReadMemoryFunc * const dma_read[] = {
- &dma_rinvalid,
- &dma_rinvalid,
- &dma_readl,
-};
-
-static CPUWriteMemoryFunc * const dma_write[] = {
- &dma_winvalid,
- &dma_winvalid,
- &dma_writel,
+static const MemoryRegionOps dma_ops = {
+ .read = dma_read,
+ .write = dma_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4
+ }
};
static int etraxfs_dmac_run(void *opaque)
};
static int etraxfs_dmac_run(void *opaque)
@@
-732,7
+739,7
@@
static void DMA_run(void *opaque)
struct fs_dma_ctrl *etraxfs_dmac = opaque;
int p = 1;
struct fs_dma_ctrl *etraxfs_dmac = opaque;
int p = 1;
- if (
vm_running
)
+ if (
runstate_is_running()
)
p = etraxfs_dmac_run(etraxfs_dmac);
if (p)
p = etraxfs_dmac_run(etraxfs_dmac);
if (p)
@@
-743,14
+750,16
@@
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
{
struct fs_dma_ctrl *ctrl = NULL;
{
struct fs_dma_ctrl *ctrl = NULL;
- ctrl =
qemu_mallocz
(sizeof *ctrl);
+ ctrl =
g_malloc0
(sizeof *ctrl);
ctrl->bh = qemu_bh_new(DMA_run, ctrl);
ctrl->nr_channels = nr_channels;
ctrl->bh = qemu_bh_new(DMA_run, ctrl);
ctrl->nr_channels = nr_channels;
- ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
+ ctrl->channels = g_malloc0(sizeof ctrl->channels[0] * nr_channels);
+
+ memory_region_init_io(&ctrl->mmio, &dma_ops, ctrl, "etraxfs-dma",
+ nr_channels * 0x2000);
+ memory_region_add_subregion(get_system_memory(), base, &ctrl->mmio);
- ctrl->map = cpu_register_io_memory(dma_read, dma_write, ctrl, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
return ctrl;
}
return ctrl;
}