+#endif
+
+#ifdef FORCE_CORTEXX1
+#define FORCE
+#define ARCHITECTURE "ARM64"
+#define SUBARCHITECTURE "CORTEXX1"
+#define SUBDIRNAME "arm64"
+#define ARCHCONFIG "-DCORTEXX1 " \
+ "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
+ "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
+ "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
+ "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
+#define LIBNAME "cortexx1"
+#define CORENAME "CORTEXX1"
+#endif
+
+#ifdef FORCE_CORTEXX2
+#define FORCE
+#define ARCHITECTURE "ARM64"
+#define SUBARCHITECTURE "CORTEXX2"
+#define SUBDIRNAME "arm64"
+#define ARCHCONFIG "-DCORTEXX2 " \
+ "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
+ "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
+ "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
+ "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
+#define LIBNAME "cortexx2"
+#define CORENAME "CORTEXX2"
+#endif
+
+#ifdef FORCE_CORTEXA510
+#define FORCE
+#define ARCHITECTURE "ARM64"
+#define SUBARCHITECTURE "CORTEXA510"
+#define SUBDIRNAME "arm64"
+#define ARCHCONFIG "-DCORTEXA510 " \
+ "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
+ "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
+ "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
+ "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
+#define LIBNAME "cortexa510"
+#define CORENAME "CORTEXA510"
+#endif
+
+#ifdef FORCE_CORTEXA710
+#define FORCE
+#define ARCHITECTURE "ARM64"
+#define SUBARCHITECTURE "CORTEXA710"
+#define SUBDIRNAME "arm64"
+#define ARCHCONFIG "-DCORTEXA710 " \
+ "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
+ "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
+ "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
+ "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 -DARMV9"
+#define LIBNAME "cortexa710"
+#define CORENAME "CORTEXA710"