+ }
+
+ /* AHI r1, i2 --- add halfword immediate */
+ else if (word_size == 4
+ && is_ri (insn, op1_ahi, op2_ahi, &r1, &i2))
+ pv_add_constant (&data->gpr[r1], i2);
+
+ /* AGHI r1, i2 --- add halfword immediate (64-bit version) */
+ else if (word_size == 8
+ && is_ri (insn, op1_aghi, op2_aghi, &r1, &i2))
+ pv_add_constant (&data->gpr[r1], i2);
+
+ /* AR r1, r2 -- add register */
+ else if (word_size == 4
+ && is_rr (insn, op_ar, &r1, &r2))
+ pv_add (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
+
+ /* AGR r1, r2 -- add register (64-bit version) */
+ else if (word_size == 8
+ && is_rre (insn, op_agr, &r1, &r2))
+ pv_add (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
+
+ /* A r1, d2(x2, b2) -- add */
+ else if (word_size == 4
+ && is_rx (insn, op_a, &r1, &d2, &x2, &b2))
+ {
+ struct prologue_value addr;
+ struct prologue_value value;
+
+ compute_x_addr (&addr, data->gpr, d2, x2, b2);
+ s390_load (&addr, 4, &value, data);
+
+ pv_add (&data->gpr[r1], &data->gpr[r1], &value);
+ }
+
+ /* AY r1, d2(x2, b2) -- add (long-displacement version) */
+ else if (word_size == 4
+ && is_rxy (insn, op1_ay, op2_ay, &r1, &d2, &x2, &b2))
+ {
+ struct prologue_value addr;
+ struct prologue_value value;
+
+ compute_x_addr (&addr, data->gpr, d2, x2, b2);
+ s390_load (&addr, 4, &value, data);
+
+ pv_add (&data->gpr[r1], &data->gpr[r1], &value);
+ }
+
+ /* AG r1, d2(x2, b2) -- add (64-bit version) */
+ else if (word_size == 8
+ && is_rxy (insn, op1_ag, op2_ag, &r1, &d2, &x2, &b2))
+ {
+ struct prologue_value addr;
+ struct prologue_value value;
+
+ compute_x_addr (&addr, data->gpr, d2, x2, b2);
+ s390_load (&addr, 8, &value, data);
+
+ pv_add (&data->gpr[r1], &data->gpr[r1], &value);
+ }
+
+ /* SR r1, r2 -- subtract register */
+ else if (word_size == 4
+ && is_rr (insn, op_sr, &r1, &r2))
+ pv_subtract (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
+
+ /* SGR r1, r2 -- subtract register (64-bit version) */
+ else if (word_size == 8
+ && is_rre (insn, op_sgr, &r1, &r2))
+ pv_subtract (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
+
+ /* S r1, d2(x2, b2) -- subtract */
+ else if (word_size == 4
+ && is_rx (insn, op_s, &r1, &d2, &x2, &b2))
+ {
+ struct prologue_value addr;
+ struct prologue_value value;
+
+ compute_x_addr (&addr, data->gpr, d2, x2, b2);
+ s390_load (&addr, 4, &value, data);
+
+ pv_subtract (&data->gpr[r1], &data->gpr[r1], &value);
+ }
+
+ /* SY r1, d2(x2, b2) -- subtract (long-displacement version) */
+ else if (word_size == 4
+ && is_rxy (insn, op1_sy, op2_sy, &r1, &d2, &x2, &b2))
+ {
+ struct prologue_value addr;
+ struct prologue_value value;
+
+ compute_x_addr (&addr, data->gpr, d2, x2, b2);
+ s390_load (&addr, 4, &value, data);
+
+ pv_subtract (&data->gpr[r1], &data->gpr[r1], &value);
+ }
+
+ /* SG r1, d2(x2, b2) -- subtract (64-bit version) */
+ else if (word_size == 8
+ && is_rxy (insn, op1_sg, op2_sg, &r1, &d2, &x2, &b2))
+ {
+ struct prologue_value addr;
+ struct prologue_value value;
+
+ compute_x_addr (&addr, data->gpr, d2, x2, b2);
+ s390_load (&addr, 8, &value, data);
+
+ pv_subtract (&data->gpr[r1], &data->gpr[r1], &value);
+ }
+
+ /* NR r1, r2 --- logical and */
+ else if (word_size == 4
+ && is_rr (insn, op_nr, &r1, &r2))
+ pv_logical_and (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
+
+ /* NGR r1, r2 >--- logical and (64-bit version) */
+ else if (word_size == 8
+ && is_rre (insn, op_ngr, &r1, &r2))
+ pv_logical_and (&data->gpr[r1], &data->gpr[r1], &data->gpr[r2]);
+
+ /* LA r1, d2(x2, b2) --- load address */
+ else if (is_rx (insn, op_la, &r1, &d2, &x2, &b2))
+ compute_x_addr (&data->gpr[r1], data->gpr, d2, x2, b2);
+
+ /* LAY r1, d2(x2, b2) --- load address (long-displacement version) */
+ else if (is_rxy (insn, op1_lay, op2_lay, &r1, &d2, &x2, &b2))
+ compute_x_addr (&data->gpr[r1], data->gpr, d2, x2, b2);