- reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
- /* derive USB PHY clock multiplexer from PLL3 */
- reg |= 1 << 26;
- __raw_writel(reg, &sc_regs->cscmr1);
-#endif
+static const struct ehci_ops mx5_ehci_ops = {
+ .powerup_fixup = mx5_ehci_powerup_fixup,
+};
+
+static int ehci_usb_of_to_plat(struct udevice *dev)
+{
+ struct usb_plat *plat = dev_get_plat(dev);
+ const char *mode;
+
+ mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
+ if (mode) {
+ if (strcmp(mode, "peripheral") == 0)
+ plat->init_type = USB_INIT_DEVICE;
+ else if (strcmp(mode, "host") == 0)
+ plat->init_type = USB_INIT_HOST;
+ else
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+ struct usb_plat *plat = dev_get_plat(dev);
+ struct usb_ehci *ehci = dev_read_addr_ptr(dev);
+ struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
+ enum usb_init_type type = plat->init_type;
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ int ret;