-#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000)
-#define MAC_CONFIG_1_TX_ENABLE (0x00000001)
-#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002)
-#define MAC_CONFIG_1_RX_ENABLE (0x00000004)
-#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008)
-#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010)
-#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020)
-#define MAC_CONFIG_1_LOOP_BACK (0x00000100)
-#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000)
-#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000)
-#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000)
-#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000)
-#define MAC_CONFIG_1_SIM_RESET (0x40000000)
-#define MAC_CONFIG_1_SOFT_RESET (0x80000000)
-
-#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004)
-#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001)
-#define MAC_CONFIG_2_CRC_ENABLE (0x00000002)
-#define MAC_CONFIG_2_PAD_CRC (0x00000004)
-#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010)
-#define MAC_CONFIG_2_HUGE_FRAME (0x00000020)
-#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8)
-#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12)
-#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */
-#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */
-
-#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010)
-
-#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020)
-#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7)
-#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010)
-#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020)
-#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000)
-
-#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024)
-#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001)
-#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002)
-
-#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028)
-#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c)
-#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030)
-
-#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034)
-#define MII_MGMT_INDICATORS_BUSY (0x00000001)
-#define MII_MGMT_INDICATORS_SCAN (0x00000002)
-#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004)
-
-#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c)
-#define INTERFACE_STATUS_LINK_FAIL (0x00000008)
-#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200)
-
-#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040)
-#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044)
-
-#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200)
-#define PORT_CONTROL_PRI (0x00000001)
-#define PORT_CONTROL_BPT (0x00010000)
-#define PORT_CONTROL_SPD (0x00040000)
-#define PORT_CONTROL_RBC (0x00080000)
-#define PORT_CONTROL_PRB (0x00200000)
-#define PORT_CONTROL_DIS (0x00400000)
-#define PORT_CONTROL_TBI (0x00800000)
-#define PORT_CONTROL_STE (0x10000000)
-#define PORT_CONTROL_ZOR (0x20000000)
-#define PORT_CONTROL_CLR (0x40000000)
-#define PORT_CONTROL_SRT (0x80000000)
-
-#define reg_TX_CONFIG(base) __REG32(base, 0x00000220)
-#define TX_CONFIG_START_Q (0x00000003)
-#define TX_CONFIG_EHP (0x00400000)
-#define TX_CONFIG_CHP (0x00800000)
-#define TX_CONFIG_RST (0x80000000)
-
-#define reg_TX_CONTROL(base) __REG32(base, 0x00000224)
-#define TX_CONTROL_GO (0x00008000)
-#define TX_CONTROL_MP (0x01000000)
-#define TX_CONTROL_EAI (0x20000000)
-#define TX_CONTROL_ABT (0x40000000)
-#define TX_CONTROL_EII (0x80000000)
-
-#define reg_TX_STATUS(base) __REG32(base, 0x00000228)
-#define TX_STATUS_QUEUE_USABLE (0x0000000f)
-#define TX_STATUS_CURR_Q (0x00000300)
-#define TX_STATUS_ACT (0x00008000)
-#define TX_STATUS_QUEUE_IDLE (0x000f0000)
-#define TX_STATUS_EOQ_PENDING (0x0f000000)
-
-#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c)
-#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f)
-#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00)
-#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
-#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
-
-#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230)
+#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000)
+#define MAC_CONFIG_1_TX_ENABLE (0x00000001)
+#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002)
+#define MAC_CONFIG_1_RX_ENABLE (0x00000004)
+#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008)
+#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010)
+#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020)
+#define MAC_CONFIG_1_LOOP_BACK (0x00000100)
+#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000)
+#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000)
+#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000)
+#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000)
+#define MAC_CONFIG_1_SIM_RESET (0x40000000)
+#define MAC_CONFIG_1_SOFT_RESET (0x80000000)
+
+#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004)
+#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001)
+#define MAC_CONFIG_2_CRC_ENABLE (0x00000002)
+#define MAC_CONFIG_2_PAD_CRC (0x00000004)
+#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010)
+#define MAC_CONFIG_2_HUGE_FRAME (0x00000020)
+#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8)
+#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12)
+#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */
+#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */
+
+#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010)
+
+#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020)
+#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7)
+#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010)
+#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020)
+#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000)
+
+#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024)
+#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001)
+#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002)
+
+#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028)
+#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c)
+#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030)
+
+#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034)
+#define MII_MGMT_INDICATORS_BUSY (0x00000001)
+#define MII_MGMT_INDICATORS_SCAN (0x00000002)
+#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004)
+
+#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c)
+#define INTERFACE_STATUS_LINK_FAIL (0x00000008)
+#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200)
+
+#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040)
+#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044)
+
+#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200)
+#define PORT_CONTROL_PRI (0x00000001)
+#define PORT_CONTROL_BPT (0x00010000)
+#define PORT_CONTROL_SPD (0x00040000)
+#define PORT_CONTROL_RBC (0x00080000)
+#define PORT_CONTROL_PRB (0x00200000)
+#define PORT_CONTROL_DIS (0x00400000)
+#define PORT_CONTROL_TBI (0x00800000)
+#define PORT_CONTROL_STE (0x10000000)
+#define PORT_CONTROL_ZOR (0x20000000)
+#define PORT_CONTROL_CLR (0x40000000)
+#define PORT_CONTROL_SRT (0x80000000)
+
+#define reg_TX_CONFIG(base) __REG32(base, 0x00000220)
+#define TX_CONFIG_START_Q (0x00000003)
+#define TX_CONFIG_EHP (0x00400000)
+#define TX_CONFIG_CHP (0x00800000)
+#define TX_CONFIG_RST (0x80000000)
+
+#define reg_TX_CONTROL(base) __REG32(base, 0x00000224)
+#define TX_CONTROL_GO (0x00008000)
+#define TX_CONTROL_MP (0x01000000)
+#define TX_CONTROL_EAI (0x20000000)
+#define TX_CONTROL_ABT (0x40000000)
+#define TX_CONTROL_EII (0x80000000)
+
+#define reg_TX_STATUS(base) __REG32(base, 0x00000228)
+#define TX_STATUS_QUEUE_USABLE (0x0000000f)
+#define TX_STATUS_CURR_Q (0x00000300)
+#define TX_STATUS_ACT (0x00008000)
+#define TX_STATUS_QUEUE_IDLE (0x000f0000)
+#define TX_STATUS_EOQ_PENDING (0x0f000000)
+
+#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c)
+#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f)
+#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00)
+#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
+#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
+
+#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230)
-#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
-#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000)
-#define TX_DIAGNOSTIC_ADDR_AI (0x80000000)
-
-#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274)
-
-#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278)
-#define TX_ERROR_STATUS (0x00000278)
-#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080)
-#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000)
-#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000)
-#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000)
-
-#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280)
-#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
-#define TX_QUEUE_0_CONFIG_BSWP (0x00000400)
-#define TX_QUEUE_0_CONFIG_WSWP (0x00000800)
-#define TX_QUEUE_0_CONFIG_AM (0x00004000)
-#define TX_QUEUE_0_CONFIG_GVI (0x00008000)
-#define TX_QUEUE_0_CONFIG_EEI (0x00010000)
-#define TX_QUEUE_0_CONFIG_ELI (0x00020000)
-#define TX_QUEUE_0_CONFIG_ENI (0x00040000)
-#define TX_QUEUE_0_CONFIG_ESI (0x00080000)
-#define TX_QUEUE_0_CONFIG_EDI (0x00100000)
-
-#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284)
-#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
-#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
-#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
-#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
-
-#define OCN_PORT_HLP 0 /* HLP Interface */
-#define OCN_PORT_PCI_X 1 /* PCI-X Interface */
+#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
+#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000)
+#define TX_DIAGNOSTIC_ADDR_AI (0x80000000)
+
+#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274)
+
+#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278)
+#define TX_ERROR_STATUS (0x00000278)
+#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f)
+#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010)
+#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020)
+#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040)
+#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080)
+#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00)
+#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000)
+#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000)
+#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000)
+#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000)
+#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000)
+#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000)
+#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000)
+#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000)
+#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000)
+#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000)
+#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000)
+#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000)
+#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000)
+#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000)
+
+#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280)
+#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
+#define TX_QUEUE_0_CONFIG_BSWP (0x00000400)
+#define TX_QUEUE_0_CONFIG_WSWP (0x00000800)
+#define TX_QUEUE_0_CONFIG_AM (0x00004000)
+#define TX_QUEUE_0_CONFIG_GVI (0x00008000)
+#define TX_QUEUE_0_CONFIG_EEI (0x00010000)
+#define TX_QUEUE_0_CONFIG_ELI (0x00020000)
+#define TX_QUEUE_0_CONFIG_ENI (0x00040000)
+#define TX_QUEUE_0_CONFIG_ESI (0x00080000)
+#define TX_QUEUE_0_CONFIG_EDI (0x00100000)
+
+#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284)
+#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
+#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
+#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
+#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
+
+#define OCN_PORT_HLP 0 /* HLP Interface */
+#define OCN_PORT_PCI_X 1 /* PCI-X Interface */
-#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */
-#define OCN_PORT_MEMORY 4 /* Memory Controller */
-#define OCN_PORT_DMA 5 /* DMA Controller */
-#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */
-#define OCN_PORT_PRINT 7 /* Print Engine Interface */
-
-#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288)
-
-#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c)
-#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
-
-#define reg_RX_CONFIG(base) __REG32(base, 0x00000320)
-#define RX_CONFIG_DEF_Q (0x00000003)
-#define RX_CONFIG_EMF (0x00000100)
-#define RX_CONFIG_EUF (0x00000200)
-#define RX_CONFIG_BFE (0x00000400)
-#define RX_CONFIG_MFE (0x00000800)
-#define RX_CONFIG_UFE (0x00001000)
-#define RX_CONFIG_SE (0x00002000)
-#define RX_CONFIG_ABF (0x00200000)
-#define RX_CONFIG_APE (0x00400000)
-#define RX_CONFIG_CHP (0x00800000)
-#define RX_CONFIG_RST (0x80000000)
-
-#define reg_RX_CONTROL(base) __REG32(base, 0x00000324)
-#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f)
-#define GE_E0_RX_CONTROL_GO (0x00008000)
-#define GE_E0_RX_CONTROL_EAI (0x20000000)
-#define GE_E0_RX_CONTROL_ABT (0x40000000)
-#define GE_E0_RX_CONTROL_EII (0x80000000)
-
-#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c)
-#define RX_EXTENDED_STATUS (0x0000032c)
-#define RX_EXTENDED_STATUS_EOQ (0x0000000f)
-#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001)
-#define RX_EXTENDED_STATUS_EOF (0x00000f00)
-#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
-#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
-
-#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330)
-
-#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370)
-#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
-#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000)
-#define RX_DIAGNOSTIC_ADDR_AI (0x80000000)
-
-#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374)
-
-#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380)
-#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
-#define RX_QUEUE_0_CONFIG_BSWP (0x00000400)
-#define RX_QUEUE_0_CONFIG_WSWP (0x00000800)
-#define RX_QUEUE_0_CONFIG_AM (0x00004000)
-#define RX_QUEUE_0_CONFIG_EEI (0x00010000)
-#define RX_QUEUE_0_CONFIG_ELI (0x00020000)
-#define RX_QUEUE_0_CONFIG_ENI (0x00040000)
-#define RX_QUEUE_0_CONFIG_ESI (0x00080000)
-#define RX_QUEUE_0_CONFIG_EDI (0x00100000)
-
-#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384)
-#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
-#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
-#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
-#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
-
-#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388)
-
-#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c)
-#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
+#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */
+#define OCN_PORT_MEMORY 4 /* Memory Controller */
+#define OCN_PORT_DMA 5 /* DMA Controller */
+#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */
+#define OCN_PORT_PRINT 7 /* Print Engine Interface */
+
+#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288)
+
+#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c)
+#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
+
+#define reg_RX_CONFIG(base) __REG32(base, 0x00000320)
+#define RX_CONFIG_DEF_Q (0x00000003)
+#define RX_CONFIG_EMF (0x00000100)
+#define RX_CONFIG_EUF (0x00000200)
+#define RX_CONFIG_BFE (0x00000400)
+#define RX_CONFIG_MFE (0x00000800)
+#define RX_CONFIG_UFE (0x00001000)
+#define RX_CONFIG_SE (0x00002000)
+#define RX_CONFIG_ABF (0x00200000)
+#define RX_CONFIG_APE (0x00400000)
+#define RX_CONFIG_CHP (0x00800000)
+#define RX_CONFIG_RST (0x80000000)
+
+#define reg_RX_CONTROL(base) __REG32(base, 0x00000324)
+#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f)
+#define GE_E0_RX_CONTROL_GO (0x00008000)
+#define GE_E0_RX_CONTROL_EAI (0x20000000)
+#define GE_E0_RX_CONTROL_ABT (0x40000000)
+#define GE_E0_RX_CONTROL_EII (0x80000000)
+
+#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c)
+#define RX_EXTENDED_STATUS (0x0000032c)
+#define RX_EXTENDED_STATUS_EOQ (0x0000000f)
+#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001)
+#define RX_EXTENDED_STATUS_EOF (0x00000f00)
+#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
+#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
+
+#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330)
+
+#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370)
+#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
+#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000)
+#define RX_DIAGNOSTIC_ADDR_AI (0x80000000)
+
+#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374)
+
+#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380)
+#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
+#define RX_QUEUE_0_CONFIG_BSWP (0x00000400)
+#define RX_QUEUE_0_CONFIG_WSWP (0x00000800)
+#define RX_QUEUE_0_CONFIG_AM (0x00004000)
+#define RX_QUEUE_0_CONFIG_EEI (0x00010000)
+#define RX_QUEUE_0_CONFIG_ELI (0x00020000)
+#define RX_QUEUE_0_CONFIG_ENI (0x00040000)
+#define RX_QUEUE_0_CONFIG_ESI (0x00080000)
+#define RX_QUEUE_0_CONFIG_EDI (0x00100000)
+
+#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384)
+#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
+#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
+#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
+#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
+
+#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388)
+
+#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c)
+#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
-#define PHY_CTRL_RESET (1 << 15)
-#define PHY_CTRL_LOOPBACK (1 << 14)
-#define PHY_CTRL_SPEED0 (1 << 13)
-#define PHY_CTRL_AN_EN (1 << 12)
-#define PHY_CTRL_PWR_DN (1 << 11)
-#define PHY_CTRL_ISOLATE (1 << 10)
-#define PHY_CTRL_RESTART_AN (1 << 9)
-#define PHY_CTRL_FULL_DUPLEX (1 << 8)
-#define PHY_CTRL_CT_EN (1 << 7)
-#define PHY_CTRL_SPEED1 (1 << 6)
-
-#define PHY_STAT_100BASE_T4 (1 << 15)
-#define PHY_STAT_100BASE_X_FD (1 << 14)
-#define PHY_STAT_100BASE_X_HD (1 << 13)
-#define PHY_STAT_10BASE_T_FD (1 << 12)
-#define PHY_STAT_10BASE_T_HD (1 << 11)
-#define PHY_STAT_100BASE_T2_FD (1 << 10)
-#define PHY_STAT_100BASE_T2_HD (1 << 9)
-#define PHY_STAT_EXT_STAT (1 << 8)
-#define PHY_STAT_RESERVED (1 << 7)
-#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */
-#define PHY_STAT_AN_COMPLETE (1 << 5)
-#define PHY_STAT_REM_FAULT (1 << 4)
-#define PHY_STAT_AN_CAP (1 << 3)
-#define PHY_STAT_LINK_UP (1 << 2)
-#define PHY_STAT_JABBER (1 << 1)
-#define PHY_STAT_EXT_CAP (1 << 0)
-
-#define TBI_CONTROL_2 0x11
-#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001
-#define TBI_CONTROL_2_ENABLE_WRAP 0x0002
-#define TBI_CONTROL_2_G_MII_MODE 0x0010
-#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020
-#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100
-#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000
-#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000
-#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000
-#define TBI_CONTROL_2_SOFT_RESET 0x8000
+#define PHY_CTRL_RESET (1 << 15)
+#define PHY_CTRL_LOOPBACK (1 << 14)
+#define PHY_CTRL_SPEED0 (1 << 13)
+#define PHY_CTRL_AN_EN (1 << 12)
+#define PHY_CTRL_PWR_DN (1 << 11)
+#define PHY_CTRL_ISOLATE (1 << 10)
+#define PHY_CTRL_RESTART_AN (1 << 9)
+#define PHY_CTRL_FULL_DUPLEX (1 << 8)
+#define PHY_CTRL_CT_EN (1 << 7)
+#define PHY_CTRL_SPEED1 (1 << 6)
+
+#define PHY_STAT_100BASE_T4 (1 << 15)
+#define PHY_STAT_100BASE_X_FD (1 << 14)
+#define PHY_STAT_100BASE_X_HD (1 << 13)
+#define PHY_STAT_10BASE_T_FD (1 << 12)
+#define PHY_STAT_10BASE_T_HD (1 << 11)
+#define PHY_STAT_100BASE_T2_FD (1 << 10)
+#define PHY_STAT_100BASE_T2_HD (1 << 9)
+#define PHY_STAT_EXT_STAT (1 << 8)
+#define PHY_STAT_RESERVED (1 << 7)
+#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */
+#define PHY_STAT_AN_COMPLETE (1 << 5)
+#define PHY_STAT_REM_FAULT (1 << 4)
+#define PHY_STAT_AN_CAP (1 << 3)
+#define PHY_STAT_LINK_UP (1 << 2)
+#define PHY_STAT_JABBER (1 << 1)
+#define PHY_STAT_EXT_CAP (1 << 0)
+
+#define TBI_CONTROL_2 0x11
+#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001
+#define TBI_CONTROL_2_ENABLE_WRAP 0x0002
+#define TBI_CONTROL_2_G_MII_MODE 0x0010
+#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020
+#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100
+#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000
+#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000
+#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000
+#define TBI_CONTROL_2_SOFT_RESET 0x8000