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Merge branch 'master' of git://git.denx.de/u-boot-arm
[platform/kernel/u-boot.git]
/
drivers
/
spi
/
mxc_spi.c
diff --git
a/drivers/spi/mxc_spi.c
b/drivers/spi/mxc_spi.c
index
d792d8d
..
9c68d7d
100644
(file)
--- a/
drivers/spi/mxc_spi.c
+++ b/
drivers/spi/mxc_spi.c
@@
-128,8
+128,8
@@
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
unsigned int max_hz, unsigned int mode)
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
- s32
pre_div = 0, post_div = 0, i,
reg_ctrl, reg_config;
- u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
+ s32 reg_ctrl, reg_config;
+ u32 ss_pol = 0, sclkpol = 0, sclkpha = 0
, pre_div = 0, post_div = 0
;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
if (max_hz == 0) {
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
if (max_hz == 0) {
@@
-137,32
+137,30
@@
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
return -1;
}
return -1;
}
- reg_ctrl = reg_read(®s->ctrl);
-
- /* Reset spi */
- reg_write(®s->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN));
- reg_write(®s->ctrl, (reg_ctrl | MXC_CSPICTRL_EN));
-
/*
/*
- * The following computation is taken directly from Freescale's code.
+ * Reset SPI and set all CSs to master mode, if toggling
+ * between slave and master mode we might see a glitch
+ * on the clock line
*/
*/
+ reg_ctrl = MXC_CSPICTRL_MODE_MASK;
+ reg_write(®s->ctrl, reg_ctrl);
+ reg_ctrl |= MXC_CSPICTRL_EN;
+ reg_write(®s->ctrl, reg_ctrl);
+
if (clk_src > max_hz) {
if (clk_src > max_hz) {
- pre_div = DIV_ROUND_UP(clk_src, max_hz);
- if (pre_div > 16) {
- post_div = pre_div / 16;
- pre_div = 15;
- }
- if (post_div != 0) {
- for (i = 0; i < 16; i++) {
- if ((1 << i) >= post_div)
- break;
- }
- if (i == 16) {
+ pre_div = (clk_src - 1) / max_hz;
+ /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
+ post_div = fls(pre_div);
+ if (post_div > 4) {
+ post_div -= 4;
+ if (post_div >= 16) {
printf("Error: no divider for the freq: %d\n",
max_hz);
return -1;
}
printf("Error: no divider for the freq: %d\n",
max_hz);
return -1;
}
- post_div = i;
+ pre_div >>= post_div;
+ } else {
+ post_div = 0;
}
}
}
}
@@
-174,9
+172,6
@@
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div);
reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div);
- /* always set to master mode */
- reg_ctrl |= 1 << (cs + 4);
-
/* We need to disable SPI before changing registers */
reg_ctrl &= ~MXC_CSPICTRL_EN;
/* We need to disable SPI before changing registers */
reg_ctrl &= ~MXC_CSPICTRL_EN;
@@
-223,7
+218,7
@@
int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
const u8 *dout, u8 *din, unsigned long flags)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
const u8 *dout, u8 *din, unsigned long flags)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
- int nbytes =
(bitlen + 7) / 8
;
+ int nbytes =
DIV_ROUND_UP(bitlen, 8)
;
u32 data, cnt, i;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
u32 data, cnt, i;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
@@
-293,7
+288,7
@@
int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
/* Transfer completed, clear any pending request */
reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
/* Transfer completed, clear any pending request */
reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
- nbytes =
(bitlen + 7) / 8
;
+ nbytes =
DIV_ROUND_UP(bitlen, 8)
;
cnt = nbytes % 32;
cnt = nbytes % 32;
@@
-329,7
+324,7
@@
int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
- int n_bytes =
(bitlen + 7) / 8
;
+ int n_bytes =
DIV_ROUND_UP(bitlen, 8)
;
int n_bits;
int ret;
u32 blk_size;
int n_bits;
int ret;
u32 blk_size;