- reg_ctrl = reg_read(®s->ctrl);
-
- /* Reset spi */
- reg_write(®s->ctrl, 0);
- reg_write(®s->ctrl, (reg_ctrl | 0x1));
+ /*
+ * Reset SPI and set all CSs to master mode, if toggling
+ * between slave and master mode we might see a glitch
+ * on the clock line
+ */
+ reg_ctrl = MXC_CSPICTRL_MODE_MASK;
+ reg_write(®s->ctrl, reg_ctrl);
+ reg_ctrl |= MXC_CSPICTRL_EN;
+ reg_write(®s->ctrl, reg_ctrl);