/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Chao Fu (B44548@freescale.com)
* Haikun Wang (B53464@freescale.com)
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Chao Fu (B44548@freescale.com)
* Haikun Wang (B53464@freescale.com)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
/* configure transfer mode */
cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
/* configure transfer mode */
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
plat->num_chipselect =
fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
plat->num_chipselect =
fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);