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dm: treewide: Rename auto_alloc_size members to be shorter
[platform/kernel/u-boot.git]
/
drivers
/
serial
/
serial_sh.c
diff --git
a/drivers/serial/serial_sh.c
b/drivers/serial/serial_sh.c
index
087785f
..
4e37ab0
100644
(file)
--- a/
drivers/serial/serial_sh.c
+++ b/
drivers/serial/serial_sh.c
@@
-1,10
+1,9
@@
+// SPDX-License-Identifier: GPL-2.0+
/*
* SuperH SCIF device driver.
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
* Copyright (C) 2002 - 2008 Paul Mundt
/*
* SuperH SCIF device driver.
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
* Copyright (C) 2002 - 2008 Paul Mundt
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
*/
#include <common.h>
@@
-16,14
+15,12
@@
#include <serial.h>
#include <linux/compiler.h>
#include <dm/platform_data/serial_sh.h>
#include <serial.h>
#include <linux/compiler.h>
#include <dm/platform_data/serial_sh.h>
+#include <linux/delay.h>
#include "serial_sh.h"
DECLARE_GLOBAL_DATA_PTR;
#include "serial_sh.h"
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_CPU_SH7760) || \
- defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786)
+#if defined(CONFIG_CPU_SH7780)
static int scif_rxfill(struct uart_port *port)
{
return sci_in(port, SCRFDR) & 0xff;
static int scif_rxfill(struct uart_port *port)
{
return sci_in(port, SCRFDR) & 0xff;
@@
-40,14
+37,6
@@
static int scif_rxfill(struct uart_port *port)
return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
}
}
return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
}
}
-#elif defined(CONFIG_ARCH_SH7372)
-static int scif_rxfill(struct uart_port *port)
-{
- if (port->type == PORT_SCIFA)
- return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
- else
- return sci_in(port, SCRFDR);
-}
#else
static int scif_rxfill(struct uart_port *port)
{
#else
static int scif_rxfill(struct uart_port *port)
{
@@
-64,6
+53,9
@@
static void sh_serial_init_generic(struct uart_port *port)
sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
sci_in(port, SCFCR);
sci_out(port, SCFCR, 0);
sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
sci_in(port, SCFCR);
sci_out(port, SCFCR, 0);
+#if defined(CONFIG_RZA1)
+ sci_out(port, SCSPTR, 0x0003);
+#endif
}
static void
}
static void
@@
-124,7
+116,10
@@
static int serial_getc_check(struct uart_port *port)
handle_error(port);
if (sci_in(port, SCLSR) & SCxSR_ORER(port))
handle_error(port);
handle_error(port);
if (sci_in(port, SCLSR) & SCxSR_ORER(port))
handle_error(port);
- return status & (SCIF_DR | SCxSR_RDxF(port));
+ status &= (SCIF_DR | SCxSR_RDxF(port));
+ if (status)
+ return status;
+ return scif_rxfill(port);
}
static int sh_serial_getc_generic(struct uart_port *port)
}
static int sh_serial_getc_generic(struct uart_port *port)
@@
-149,7
+144,7
@@
static int sh_serial_getc_generic(struct uart_port *port)
return ch;
}
return ch;
}
-#if
def CONFIG_DM_SERIAL
+#if
CONFIG_IS_ENABLED(DM_SERIAL)
static int sh_serial_pending(struct udevice *dev, bool input)
{
static int sh_serial_pending(struct udevice *dev, bool input)
{
@@
-204,7
+199,7
@@
static const struct dm_serial_ops sh_serial_ops = {
.setbrg = sh_serial_setbrg,
};
.setbrg = sh_serial_setbrg,
};
-#if
def CONFIG_OF_CONTROL
+#if
CONFIG_IS_ENABLED(OF_CONTROL)
static const struct udevice_id sh_serial_id[] ={
{.compatible = "renesas,sci", .data = PORT_SCI},
{.compatible = "renesas,scif", .data = PORT_SCIF},
static const struct udevice_id sh_serial_id[] ={
{.compatible = "renesas,sci", .data = PORT_SCI},
{.compatible = "renesas,scif", .data = PORT_SCIF},
@@
-219,18
+214,21
@@
static int sh_serial_ofdata_to_platdata(struct udevice *dev)
fdt_addr_t addr;
int ret;
fdt_addr_t addr;
int ret;
- addr =
fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg"
);
- if (
addr == FDT_ADDR_T_NONE
)
+ addr =
dev_read_addr(dev
);
+ if (
!addr
)
return -EINVAL;
plat->base = addr;
ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
return -EINVAL;
plat->base = addr;
ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
- if (!ret)
- plat->clk = clk_get_rate(&sh_serial_clk);
- else
+ if (!ret) {
+ ret = clk_enable(&sh_serial_clk);
+ if (!ret)
+ plat->clk = clk_get_rate(&sh_serial_clk);
+ } else {
plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock", 1);
plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock", 1);
+ }
plat->type = dev_get_driver_data(dev);
return 0;
plat->type = dev_get_driver_data(dev);
return 0;
@@
-242,11
+240,13
@@
U_BOOT_DRIVER(serial_sh) = {
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(sh_serial_id),
.ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
.id = UCLASS_SERIAL,
.of_match = of_match_ptr(sh_serial_id),
.ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
- .platdata_auto
_alloc_size
= sizeof(struct sh_serial_platdata),
+ .platdata_auto
= sizeof(struct sh_serial_platdata),
.probe = sh_serial_probe,
.ops = &sh_serial_ops,
.probe = sh_serial_probe,
.ops = &sh_serial_ops,
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
.flags = DM_FLAG_PRE_RELOC,
.flags = DM_FLAG_PRE_RELOC,
- .priv_auto_alloc_size = sizeof(struct uart_port),
+#endif
+ .priv_auto = sizeof(struct uart_port),
};
#else /* CONFIG_DM_SERIAL */
};
#else /* CONFIG_DM_SERIAL */
@@
-267,6
+267,8
@@
U_BOOT_DRIVER(serial_sh) = {
# define SCIF_BASE SCIF6_BASE
#elif defined(CONFIG_CONS_SCIF7)
# define SCIF_BASE SCIF7_BASE
# define SCIF_BASE SCIF6_BASE
#elif defined(CONFIG_CONS_SCIF7)
# define SCIF_BASE SCIF7_BASE
+#elif defined(CONFIG_CONS_SCIFA0)
+# define SCIF_BASE SCIFA0_BASE
#else
# error "Default SCIF doesn't set....."
#endif
#else
# error "Default SCIF doesn't set....."
#endif