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core: remap: fix regmap_init_mem_plat() reg size handeling
[platform/kernel/u-boot.git]
/
drivers
/
ram
/
rockchip
/
sdram_rk3188.c
diff --git
a/drivers/ram/rockchip/sdram_rk3188.c
b/drivers/ram/rockchip/sdram_rk3188.c
index
9b5eb38
..
ad9f936
100644
(file)
--- a/
drivers/ram/rockchip/sdram_rk3188.c
+++ b/
drivers/ram/rockchip/sdram_rk3188.c
@@
-12,6
+12,8
@@
#include <dt-structs.h>
#include <errno.h>
#include <hang.h>
#include <dt-structs.h>
#include <errno.h>
#include <hang.h>
+#include <init.h>
+#include <log.h>
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
@@
-23,6
+25,7
@@
#include <asm/arch-rockchip/pmu_rk3188.h>
#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3188.h>
#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3288.h>
+#include <linux/delay.h>
#include <linux/err.h>
struct chan_info {
#include <linux/err.h>
struct chan_info {
@@
-635,12
+638,12
@@
static int sdram_col_row_detect(struct dram_info *dram, int channel,
/* Detect col */
for (col = 11; col >= 9; col--) {
/* Detect col */
for (col = 11; col >= 9; col--) {
- writel(0, C
ONFI
G_SYS_SDRAM_BASE);
- addr = C
ONFI
G_SYS_SDRAM_BASE +
+ writel(0, C
F
G_SYS_SDRAM_BASE);
+ addr = C
F
G_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(C
ONFI
G_SYS_SDRAM_BASE) == 0))
+ (readl(C
F
G_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
break;
}
if (col == 8) {
@@
-657,11
+660,11
@@
static int sdram_col_row_detect(struct dram_info *dram, int channel,
move_to_access_state(chan);
/* Detect row, max 15,min13 in rk3188*/
for (row = 16; row >= 13; row--) {
move_to_access_state(chan);
/* Detect row, max 15,min13 in rk3188*/
for (row = 16; row >= 13; row--) {
- writel(0, C
ONFI
G_SYS_SDRAM_BASE);
- addr = C
ONFI
G_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(0, C
F
G_SYS_SDRAM_BASE);
+ addr = C
F
G_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(C
ONFI
G_SYS_SDRAM_BASE) == 0))
+ (readl(C
F
G_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
break;
}
if (row == 12) {
@@
-759,7
+762,7
@@
static int sdram_init(struct dram_info *dram,
* CS1, n=2
* CS0 & CS1, n = 3
*/
* CS1, n=2
* CS0 & CS1, n = 3
*/
- sdram_params->ch[channel].rank = 2
,
+ sdram_params->ch[channel].rank = 2
;
clrsetbits_le32(&publ->pgcr, 0xF << 18,
(sdram_params->ch[channel].rank | 1) << 18);
clrsetbits_le32(&publ->pgcr, 0xF << 18,
(sdram_params->ch[channel].rank | 1) << 18);
@@
-806,17
+809,19
@@
error:
static int setup_sdram(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
static int setup_sdram(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
- struct rk3188_sdram_params *params = dev_get_plat
data
(dev);
+ struct rk3188_sdram_params *params = dev_get_plat(dev);
return sdram_init(priv, params);
}
return sdram_init(priv, params);
}
-static int rk3188_dmc_of
data_to_platdata
(struct udevice *dev)
+static int rk3188_dmc_of
_to_plat
(struct udevice *dev)
{
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- struct rk3188_sdram_params *params = dev_get_platdata(dev);
+ struct rk3188_sdram_params *params = dev_get_plat(dev);
int ret;
int ret;
+ if (!CONFIG_IS_ENABLED(OF_REAL))
+ return 0;
+
/* rk3188 supports only one-channel */
params->num_channels = 1;
ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
/* rk3188 supports only one-channel */
params->num_channels = 1;
ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
@@
-843,16
+848,15
@@
static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
if (ret)
return ret;
ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
if (ret)
return ret;
-#endif
return 0;
}
#endif /* CONFIG_SPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
return 0;
}
#endif /* CONFIG_SPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_plat
data
(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
{
{
- struct rk3188_sdram_params *plat = dev_get_plat
data
(dev);
+ struct rk3188_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
int ret;
struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
int ret;
@@
-863,9
+867,8
@@
static int conv_of_platdata(struct udevice *dev)
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* rk3188 supports dual-channel, set default channel num to 2 */
plat->num_channels = 1;
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* rk3188 supports dual-channel, set default channel num to 2 */
plat->num_channels = 1;
- ret = regmap_init_mem_platdata(dev, of_plat->reg,
- ARRAY_SIZE(of_plat->reg) / 2,
- &plat->map);
+ ret = regmap_init_mem_plat(dev, of_plat->reg, sizeof(of_plat->reg[0]),
+ ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
if (ret)
return ret;
if (ret)
return ret;
@@
-876,7
+879,7
@@
static int conv_of_platdata(struct udevice *dev)
static int rk3188_dmc_probe(struct udevice *dev)
{
#ifdef CONFIG_SPL_BUILD
static int rk3188_dmc_probe(struct udevice *dev)
{
#ifdef CONFIG_SPL_BUILD
- struct rk3188_sdram_params *plat = dev_get_plat
data
(dev);
+ struct rk3188_sdram_params *plat = dev_get_plat(dev);
struct regmap *map;
struct udevice *dev_clk;
int ret;
struct regmap *map;
struct udevice *dev_clk;
int ret;
@@
-887,7
+890,7
@@
static int rk3188_dmc_probe(struct udevice *dev)
#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- ret = conv_of_plat
data
(dev);
+ ret = conv_of_plat(dev);
if (ret)
return ret;
#endif
if (ret)
return ret;
#endif
@@
-916,7
+919,7
@@
static int rk3188_dmc_probe(struct udevice *dev)
if (ret)
return ret;
#else
if (ret)
return ret;
#else
- priv->info.base = C
ONFI
G_SYS_SDRAM_BASE;
+ priv->info.base = C
F
G_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->pmu->sys_reg[2]);
#endif
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->pmu->sys_reg[2]);
#endif
@@
-942,17
+945,17
@@
static const struct udevice_id rk3188_dmc_ids[] = {
{ }
};
{ }
};
-U_BOOT_DRIVER(
dmc_rk3188
) = {
+U_BOOT_DRIVER(
rockchip_rk3188_dmc
) = {
.name = "rockchip_rk3188_dmc",
.id = UCLASS_RAM,
.of_match = rk3188_dmc_ids,
.ops = &rk3188_dmc_ops,
#ifdef CONFIG_SPL_BUILD
.name = "rockchip_rk3188_dmc",
.id = UCLASS_RAM,
.of_match = rk3188_dmc_ids,
.ops = &rk3188_dmc_ops,
#ifdef CONFIG_SPL_BUILD
- .of
data_to_platdata = rk3188_dmc_ofdata_to_platdata
,
+ .of
_to_plat = rk3188_dmc_of_to_plat
,
#endif
.probe = rk3188_dmc_probe,
#endif
.probe = rk3188_dmc_probe,
- .priv_auto
_alloc_size
= sizeof(struct dram_info),
+ .priv_auto
= sizeof(struct dram_info),
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_BUILD
- .plat
data_auto_alloc_size
= sizeof(struct rk3188_sdram_params),
+ .plat
_auto
= sizeof(struct rk3188_sdram_params),
#endif
};
#endif
};