+static void u2_phy_instance_init(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+
+ /* switch to USB function, and enable usb pll */
+ clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
+ P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
+ P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
+
+ clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
+ setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
+
+ /* disable switch 100uA current to SSUSB */
+ clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
+
+ clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
+
+ /* DP/DM BC1.1 path Disable */
+ clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
+ PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
+ PA6_RG_U2_SQTH_VAL(2));
+
+ /* set HS slew rate */
+ clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
+ PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
+
+ dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
+}
+
+static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+
+ clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
+ P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
+
+ /* OTG Enable */
+ setbits_le32(u2_banks->com + U3P_USBPHYACR6,
+ PA6_RG_U2_OTG_VBUSCMP_EN);
+
+ clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
+ P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
+
+ dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
+}
+
+static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+
+ clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
+ P2C_RG_XCVRSEL | P2C_RG_DATAIN);
+
+ /* OTG Disable */
+ clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
+ PA6_RG_U2_OTG_VBUSCMP_EN);
+
+ clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
+ P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);
+
+ dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
+}
+
+static void u3_phy_instance_init(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ /* gating PCIe Analog XTAL clock */
+ setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
+ XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
+
+ /* gating XSQ */
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
+ P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
+
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
+ P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
+
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
+ P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
+
+ clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
+ P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
+ P3D_RG_CDR_BIR_LTD0_VAL(0xc) |
+ P3D_RG_CDR_BIR_LTD1_VAL(0x3));
+
+ clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
+ P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
+
+ clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
+ P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
+
+ clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
+ P3D_RG_RXDET_STB2_SET_P3,
+ P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
+
+ dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
+}
+