+ if (pcie->l1ss) {
+ /*
+ * Enable CLKREQ# signalling include L1 Substate control of
+ * the CLKREQ# signal and the external reference clock buffer.
+ * meet requirement for Endpoints that require CLKREQ#
+ * assertion to clock active within 400ns.
+ */
+ tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
+ tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
+ } else {
+ /*
+ * Refclk from RC should be gated with CLKREQ# input when
+ * ASPM L0s,L1 is enabled => setting the CLKREQ_DEBUG_ENABLE
+ * field to 1.
+ */
+ tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
+ tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
+ }