-enum RTL8139_registers {
- MAC0=0, /* Ethernet hardware address. */
- MAR0=8, /* Multicast filter. */
- TxStatus0=0x10, /* Transmit status (four 32bit registers). */
- TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
- RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
- ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
- IntrMask=0x3C, IntrStatus=0x3E,
- TxConfig=0x40, RxConfig=0x44,
- Timer=0x48, /* general-purpose counter. */
- RxMissed=0x4C, /* 24 bits valid, write clears. */
- Cfg9346=0x50, Config0=0x51, Config1=0x52,
- TimerIntrReg=0x54, /* intr if gp counter reaches this value */
- MediaStatus=0x58,
- Config3=0x59,
- MultiIntr=0x5C,
- RevisionID=0x5E, /* revision of the RTL8139 chip */
- TxSummary=0x60,
- MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
- NWayExpansion=0x6A,
- DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
- NWayTestReg=0x70,
- RxCnt=0x72, /* packet received counter */
- CSCR=0x74, /* chip status and configuration register */
- PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
- /* from 0x84 onwards are a number of power management/wakeup frame
- * definitions we will probably never need to know about. */
-};
-
-enum ChipCmdBits {
- CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
-
-/* Interrupt register bits, using my own meaningful names. */
-enum IntrStatusBits {
- PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
- RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
- TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
-};
-enum TxStatusBits {
- TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
- TxOutOfWindow=0x20000000, TxAborted=0x40000000,
- TxCarrierLost=0x80000000,
-};
-enum RxStatusBits {
- RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
- RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
- RxBadAlign=0x0002, RxStatusOK=0x0001,
-};
-
-enum MediaStatusBits {
- MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
- MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
-};
-
-enum MIIBMCRBits {
- BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
- BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
-};
-
-enum CSCRBits {
- CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
- CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
- CSCR_LinkDownCmd=0x0f3c0,
-};
-
-/* Bits in RxConfig. */
-enum rx_mode_bits {
- RxCfgWrap=0x80,
- AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
- AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
-};
+/* Ethernet hardware address. */
+#define RTL_REG_MAC0 0x00
+/* Multicast filter. */
+#define RTL_REG_MAR0 0x08
+/* Transmit status (four 32bit registers). */
+#define RTL_REG_TXSTATUS0 0x10
+/* Tx descriptors (also four 32bit). */
+#define RTL_REG_TXADDR0 0x20
+#define RTL_REG_RXBUF 0x30
+#define RTL_REG_RXEARLYCNT 0x34
+#define RTL_REG_RXEARLYSTATUS 0x36
+#define RTL_REG_CHIPCMD 0x37
+#define RTL_REG_CHIPCMD_CMDRESET BIT(4)
+#define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
+#define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
+#define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
+#define RTL_REG_RXBUFPTR 0x38
+#define RTL_REG_RXBUFADDR 0x3A
+#define RTL_REG_INTRMASK 0x3C
+#define RTL_REG_INTRSTATUS 0x3E
+#define RTL_REG_INTRSTATUS_PCIERR BIT(15)
+#define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
+#define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
+#define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
+#define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
+#define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
+#define RTL_REG_INTRSTATUS_TXERR BIT(3)
+#define RTL_REG_INTRSTATUS_TXOK BIT(2)
+#define RTL_REG_INTRSTATUS_RXERR BIT(1)
+#define RTL_REG_INTRSTATUS_RXOK BIT(0)
+#define RTL_REG_TXCONFIG 0x40
+#define RTL_REG_RXCONFIG 0x44
+#define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
+#define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
+#define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
+#define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
+#define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
+#define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
+#define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
+/* general-purpose counter. */
+#define RTL_REG_TIMER 0x48
+/* 24 bits valid, write clears. */
+#define RTL_REG_RXMISSED 0x4C
+#define RTL_REG_CFG9346 0x50
+#define RTL_REG_CONFIG0 0x51
+#define RTL_REG_CONFIG1 0x52
+/* intr if gp counter reaches this value */
+#define RTL_REG_TIMERINTRREG 0x54
+#define RTL_REG_MEDIASTATUS 0x58
+#define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
+#define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
+#define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
+#define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
+#define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
+#define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
+#define RTL_REG_CONFIG3 0x59
+#define RTL_REG_MULTIINTR 0x5C
+/* revision of the RTL8139 chip */
+#define RTL_REG_REVISIONID 0x5E
+#define RTL_REG_TXSUMMARY 0x60
+#define RTL_REG_MII_BMCR 0x62
+#define RTL_REG_MII_BMSR 0x64
+#define RTL_REG_NWAYADVERT 0x66
+#define RTL_REG_NWAYLPAR 0x68
+#define RTL_REG_NWAYEXPANSION 0x6A
+#define RTL_REG_DISCONNECTCNT 0x6C
+#define RTL_REG_FALSECARRIERCNT 0x6E
+#define RTL_REG_NWAYTESTREG 0x70
+/* packet received counter */
+#define RTL_REG_RXCNT 0x72
+/* chip status and configuration register */
+#define RTL_REG_CSCR 0x74
+#define RTL_REG_PHYPARM1 0x78
+#define RTL_REG_TWISTERPARM 0x7c
+/* undocumented */
+#define RTL_REG_PHYPARM2 0x80
+/*
+ * from 0x84 onwards are a number of power management/wakeup frame
+ * definitions we will probably never need to know about.
+ */