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Merge tag 'v2021.01-rc5' into next
[platform/kernel/u-boot.git]
/
drivers
/
mtd
/
stm32_flash.c
diff --git
a/drivers/mtd/stm32_flash.c
b/drivers/mtd/stm32_flash.c
index
e16b6cd
..
95afa2d
100644
(file)
--- a/
drivers/mtd/stm32_flash.c
+++ b/
drivers/mtd/stm32_flash.c
@@
-1,23
+1,23
@@
+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
*/
#include <common.h>
+#include <flash.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include "stm32_flash.h"
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include "stm32_flash.h"
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-#define STM32_FLASH
((struct stm32_flash_regs *)
FLASH_CNTL_BASE)
+#define STM32_FLASH
((struct stm32_flash_regs *)STM32_
FLASH_CNTL_BASE)
void stm32_flash_latency_cfg(int latency)
{
/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
void stm32_flash_latency_cfg(int latency)
{
/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
- writel(FLASH_ACR_WS(
5
) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
+ writel(FLASH_ACR_WS(
latency
) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
| FLASH_ACR_DCEN, &STM32_FLASH->acr);
}
| FLASH_ACR_DCEN, &STM32_FLASH->acr);
}