+ /*
+ * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
+ * If CLK_CO_PHASE_270 is used, it's more stable than other.
+ * Other SoCs use CLK_CO_PHASE_180 by default.
+ * It needs to find what is a proper value about each SoCs.
+ */
+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
+ meson_mmc_clk |= CLK_CO_PHASE_270;
+ else
+ meson_mmc_clk |= CLK_CO_PHASE_180;