+#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
+ if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+ /* if it's RDIMM */
+ if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+ continue;
+ set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL(i) |
+ 0x070000ed,
+ MD_CNTL_MD_EN);
+ udelay(1);
+ }
+ }
+
+ ddr_out32(&ddr->err_disable,
+ regs->err_disable & ~DDR_ERR_DISABLE_APED);
+ }
+#endif
+ /* Restore D_INIT */
+ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+#endif
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
+ /* Erratum applies when accumulated ECC is used, or DBI is enabled */
+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
+ if (has_erratum_a008378()) {
+ if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+ IS_DBI(regs->ddr_sdram_cfg_3)) {
+ val32 = ddr_in32(&ddr->debug[28]);
+ val32 |= (0x9 << 20);
+ ddr_out32(&ddr->debug[28], val32);
+ }
+ debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
+ }
+#endif
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008109)
+ val32 = ddr_in32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */
+ ddr_out32(&ddr->sdram_cfg_2, val32);
+
+ val32 = ddr_in32(&ddr->debug[18]) | 0x2;
+ ddr_out32(&ddr->debug[18], val32);
+
+ ddr_out32(&ddr->debug[28], 0x30000000);
+ debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+ val32 = ddr_in32(&ddr->debug[28]);
+ val32 &= 0xff0fff00;
+ if (ddr_freq <= 1333)
+ val32 |= 0x0080006a;
+ else if (ddr_freq <= 1600)
+ val32 |= 0x0070006f;
+ else if (ddr_freq <= 1867)
+ val32 |= 0x00700076;
+ else if (ddr_freq <= 2133)
+ val32 |= 0x0060007b;
+
+ ddr_out32(&ddr->debug[28], val32);
+ debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
+#endif
+