- /* Configure port C pins to disable External Loopback
- */
- immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
- immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
- immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
- immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
-#endif /* PC_ENET_LBK */
-
- /* Configure port C pins to enable CLSN and RENA.
- */
- immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
- immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
- immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
-
- /* Configure port A for TCLK and RCLK.
- */
- immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
- immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
-
- /*
- * Configure Serial Interface clock routing -- see section 16.7.5.3
- * First, clear all SCC bits to zero, then set the ones we want.
- */
-
- immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
- immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
-
-
- /*
- * Initialize SDCR -- see section 16.9.23.7
- * SDMA configuration register
- */
- immr->im_siu_conf.sc_sdcr = 0x01;
-
-
- /*
- * Setup SCC Ethernet Parameter RAM
- */
-
- pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
- pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
-
- pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
-
- pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
- pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
-
- /*
- * Setup Receiver Buffer Descriptors (13.14.24.18)
- * Settings:
- * Empty, Wrap
- */
-
- for (i = 0; i < PKTBUFSRX; i++)
- {
- rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
- rtx->rxbd[i].cbd_datlen = 0; /* Reset */
- rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
- }
-
- rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
- /*
- * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
- * Settings:
- * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
- */
-
- for (i = 0; i < TX_BUF_CNT; i++)
- {
- rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
- rtx->txbd[i].cbd_datlen = 0; /* Reset */
- rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
- }
-
- rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
- /*
- * Enter Command: Initialize Rx Params for SCC
- */
-
- do { /* Spin until ready to issue command */
- __asm__ ("eieio");
- } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
- /* Issue command */
- immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
- do { /* Spin until command processed */
- __asm__ ("eieio");
- } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
-
- /*
- * Ethernet Specific Parameter RAM
- * see table 13-16, pg. 660,
- * pg. 681 (example with suggested settings)
- */
-
- pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
- pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
- pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
- pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
- pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
- pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
-
- pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
- pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
- pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
-
- pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
- pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
-
- pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
- pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
- pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
- pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
+ /* Configure port C pins to disable External Loopback
+ */
+ immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
+ immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
+ immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
+ immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
+#endif /* PC_ENET_LBK */
+
+ /* Configure port C pins to enable CLSN and RENA.
+ */
+ immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
+ immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
+ immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
+
+ /* Configure port A for TCLK and RCLK.
+ */
+ immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
+ immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
+
+ /*
+ * Configure Serial Interface clock routing -- see section 16.7.5.3
+ * First, clear all SCC bits to zero, then set the ones we want.
+ */
+
+ immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
+ immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
+
+
+ /*
+ * Initialize SDCR -- see section 16.9.23.7
+ * SDMA configuration register
+ */
+ immr->im_siu_conf.sc_sdcr = 0x01;
+
+
+ /*
+ * Setup SCC Ethernet Parameter RAM
+ */
+
+ pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
+ pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
+
+ pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
+
+ pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
+ pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
+
+ /*
+ * Setup Receiver Buffer Descriptors (13.14.24.18)
+ * Settings:
+ * Empty, Wrap
+ */
+
+ for (i = 0; i < PKTBUFSRX; i++) {
+ rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+ rtx->rxbd[i].cbd_datlen = 0; /* Reset */
+ rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
+ }
+
+ rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
+
+ /*
+ * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
+ * Settings:
+ * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
+ */
+
+ for (i = 0; i < TX_BUF_CNT; i++) {
+ rtx->txbd[i].cbd_sc =
+ (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
+ rtx->txbd[i].cbd_datlen = 0; /* Reset */
+ rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
+ }
+
+ rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
+
+ /*
+ * Enter Command: Initialize Rx Params for SCC
+ */
+
+ do { /* Spin until ready to issue command */
+ __asm__ ("eieio");
+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+ /* Issue command */
+ immr->im_cpm.cp_cpcr =
+ ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
+ do { /* Spin until command processed */
+ __asm__ ("eieio");
+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+
+ /*
+ * Ethernet Specific Parameter RAM
+ * see table 13-16, pg. 660,
+ * pg. 681 (example with suggested settings)
+ */
+
+ pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
+ pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
+ pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
+ pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
+ pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
+ pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
+
+ pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
+ pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
+ pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
+
+ pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
+ pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
+
+ pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
+ pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
+ pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
+ pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */