+dnl ********************************
+dnl *** g_atomic_* tests for gcc ***
+dnl ********************************
+
+AC_MSG_CHECKING([whether to use assembler code for atomic operations])
+
+if test x"$GCC" = xyes; then
+ case $host_cpu in
+ i386)
+ AC_MSG_RESULT([none])
+ glib_memory_barrier_needed=no
+ ;;
+ i?86)
+ AC_MSG_RESULT([i486])
+ AC_DEFINE_UNQUOTED(G_ATOMIC_I486, 1,
+ [i486 atomic implementation])
+ glib_memory_barrier_needed=no
+ ;;
+ sparc*)
+ SPARCV9_WARNING="Try to rerun configure with CFLAGS='-mcpu=v9',
+ when you are using a sparc with v9 instruction set (most
+ sparcs nowadays). This will make the code for atomic
+ operations much faster. The resulting code will not run
+ on very old sparcs though."
+
+ AC_LINK_IFELSE([[
+ main ()
+ {
+ int tmp1, tmp2, tmp3;
+ __asm__ __volatile__("casx [%2], %0, %1"
+ : "=&r" (tmp1), "=&r" (tmp2) : "r" (&tmp3));
+ }]],
+ AC_MSG_RESULT([sparcv9])
+ AC_DEFINE_UNQUOTED(G_ATOMIC_SPARCV9, 1,
+ [sparcv9 atomic implementation]),
+ AC_MSG_RESULT([no])
+ AC_MSG_WARN([[$SPARCV9_WARNING]]))
+ glib_memory_barrier_needed=yes
+ ;;
+ alpha*)
+ AC_MSG_RESULT([alpha])
+ AC_DEFINE_UNQUOTED(G_ATOMIC_ALPHA, 1,
+ [alpha atomic implementation])
+ glib_memory_barrier_needed=yes
+ ;;
+ x86_64)
+ AC_MSG_RESULT([x86_64])
+ AC_DEFINE_UNQUOTED(G_ATOMIC_X86_64, 1,
+ [x86_64 atomic implementation])
+ glib_memory_barrier_needed=no
+ ;;
+ powerpc*)
+ AC_MSG_RESULT([powerpc])
+ AC_DEFINE_UNQUOTED(G_ATOMIC_POWERPC, 1,
+ [powerpc atomic implementation])
+ glib_memory_barrier_needed=yes
+ ;;
+ ia64)
+ AC_MSG_RESULT([ia64])
+ AC_DEFINE_UNQUOTED(G_ATOMIC_IA64, 1,
+ [ia64 atomic implementation])
+ glib_memory_barrier_needed=yes
+ ;;
+ *)
+ AC_MSG_RESULT([none])
+ glib_memory_barrier_needed=yes
+ ;;
+ esac
+fi
+