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rename CFG_ macros to CONFIG_SYS
[platform/kernel/u-boot.git]
/
common
/
virtex2.c
diff --git
a/common/virtex2.c
b/common/virtex2.c
index
52da1b2
..
50d0921
100644
(file)
--- a/
common/virtex2.c
+++ b/
common/virtex2.c
@@
-43,34
+43,34
@@
/*
* If the SelectMap interface can be overrun by the processor, define
/*
* If the SelectMap interface can be overrun by the processor, define
- * C
FG
_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
+ * C
ONFIG_SYS
_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
* file and add board-specific support for checking BUSY status. By default,
* assume that the SelectMap interface cannot be overrun.
*/
* file and add board-specific support for checking BUSY status. By default,
* assume that the SelectMap interface cannot be overrun.
*/
-#ifndef C
FG
_FPGA_CHECK_BUSY
-#undef C
FG
_FPGA_CHECK_BUSY
+#ifndef C
ONFIG_SYS
_FPGA_CHECK_BUSY
+#undef C
ONFIG_SYS
_FPGA_CHECK_BUSY
#endif
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif
#endif
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif
-#ifndef C
FG
_FPGA_PROG_FEEDBACK
-#define C
FG
_FPGA_PROG_FEEDBACK
+#ifndef C
ONFIG_SYS
_FPGA_PROG_FEEDBACK
+#define C
ONFIG_SYS
_FPGA_PROG_FEEDBACK
#endif
/*
* Don't allow config cycle to be interrupted
*/
#endif
/*
* Don't allow config cycle to be interrupted
*/
-#ifndef C
FG
_FPGA_CHECK_CTRLC
-#undef C
FG
_FPGA_CHECK_CTRLC
+#ifndef C
ONFIG_SYS
_FPGA_CHECK_CTRLC
+#undef C
ONFIG_SYS
_FPGA_CHECK_CTRLC
#endif
/*
* Check for errors during configuration by default
*/
#endif
/*
* Check for errors during configuration by default
*/
-#ifndef C
FG
_FPGA_CHECK_ERROR
-#define C
FG
_FPGA_CHECK_ERROR
+#ifndef C
ONFIG_SYS
_FPGA_CHECK_ERROR
+#define C
ONFIG_SYS
_FPGA_CHECK_ERROR
#endif
/*
#endif
/*
@@
-81,8
+81,8
@@
* which yields 11.44 mS. So let's make it bigger in order to handle
* an XC2V1000, if anyone can ever get ahold of one.
*/
* which yields 11.44 mS. So let's make it bigger in order to handle
* an XC2V1000, if anyone can ever get ahold of one.
*/
-#ifndef C
FG
_FPGA_WAIT_INIT
-#define C
FG_FPGA_WAIT_INIT CFG_HZ/2
/* 500 ms */
+#ifndef C
ONFIG_SYS
_FPGA_WAIT_INIT
+#define C
ONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2
/* 500 ms */
#endif
/*
#endif
/*
@@
-90,15
+90,15
@@
* This is normally not necessary since for most reasonable configuration
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/
* This is normally not necessary since for most reasonable configuration
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/
-#ifndef C
FG
_FPGA_WAIT_BUSY
-#define C
FG_FPGA_WAIT_BUSY CFG_HZ/200
/* 5 ms*/
+#ifndef C
ONFIG_SYS
_FPGA_WAIT_BUSY
+#define C
ONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200
/* 5 ms*/
#endif
/* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written.
*/
#endif
/* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written.
*/
-#ifndef C
FG
_FPGA_WAIT_CONFIG
-#define C
FG_FPGA_WAIT_CONFIG CFG_HZ/5
/* 200 ms */
+#ifndef C
ONFIG_SYS
_FPGA_WAIT_CONFIG
+#define C
ONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5
/* 200 ms */
#endif
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize);
#endif
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize);
@@
-232,7
+232,7
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
fn->busy, fn->abort, fn->post);
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
fn->busy, fn->abort, fn->post);
-#ifdef C
FG
_FPGA_PROG_FEEDBACK
+#ifdef C
ONFIG_SYS
_FPGA_PROG_FEEDBACK
printf ("Initializing FPGA Device %d...\n", cookie);
#endif
/*
printf ("Initializing FPGA Device %d...\n", cookie);
#endif
/*
@@
-252,10
+252,10
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
udelay (10);
ts = get_timer (0);
do {
udelay (10);
ts = get_timer (0);
do {
- if (get_timer (ts) > C
FG
_FPGA_WAIT_INIT) {
+ if (get_timer (ts) > C
ONFIG_SYS
_FPGA_WAIT_INIT) {
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to assert.\n", __FUNCTION__, __LINE__,
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to assert.\n", __FUNCTION__, __LINE__,
- C
FG
_FPGA_WAIT_INIT);
+ C
ONFIG_SYS
_FPGA_WAIT_INIT);
(*fn->abort) (cookie);
return FPGA_FAIL;
}
(*fn->abort) (cookie);
return FPGA_FAIL;
}
@@
-271,10
+271,10
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
ts = get_timer (0);
do {
CONFIG_FPGA_DELAY ();
ts = get_timer (0);
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > C
FG
_FPGA_WAIT_INIT) {
+ if (get_timer (ts) > C
ONFIG_SYS
_FPGA_WAIT_INIT) {
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to deassert.\n", __FUNCTION__, __LINE__,
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to deassert.\n", __FUNCTION__, __LINE__,
- C
FG
_FPGA_WAIT_INIT);
+ C
ONFIG_SYS
_FPGA_WAIT_INIT);
(*fn->abort) (cookie);
return FPGA_FAIL;
}
(*fn->abort) (cookie);
return FPGA_FAIL;
}
@@
-289,7
+289,7
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
* Load the data byte by byte
*/
while (bytecount < bsize) {
* Load the data byte by byte
*/
while (bytecount < bsize) {
-#ifdef C
FG
_FPGA_CHECK_CTRLC
+#ifdef C
ONFIG_SYS
_FPGA_CHECK_CTRLC
if (ctrlc ()) {
(*fn->abort) (cookie);
return FPGA_FAIL;
if (ctrlc ()) {
(*fn->abort) (cookie);
return FPGA_FAIL;
@@
-302,7
+302,7
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
break;
}
break;
}
-#ifdef C
FG
_FPGA_CHECK_ERROR
+#ifdef C
ONFIG_SYS
_FPGA_CHECK_ERROR
if ((*fn->init) (cookie)) {
printf ("\n%s:%d: ** Error: INIT asserted during"
" configuration\n", __FUNCTION__, __LINE__);
if ((*fn->init) (cookie)) {
printf ("\n%s:%d: ** Error: INIT asserted during"
" configuration\n", __FUNCTION__, __LINE__);
@@
-323,20
+323,20
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie);
-#ifdef C
FG
_FPGA_CHECK_BUSY
+#ifdef C
ONFIG_SYS
_FPGA_CHECK_BUSY
ts = get_timer (0);
while ((*fn->busy) (cookie)) {
ts = get_timer (0);
while ((*fn->busy) (cookie)) {
- if (get_timer (ts) > C
FG
_FPGA_WAIT_BUSY) {
+ if (get_timer (ts) > C
ONFIG_SYS
_FPGA_WAIT_BUSY) {
printf ("%s:%d: ** Timeout after %d ticks waiting for"
" BUSY to deassert\n",
printf ("%s:%d: ** Timeout after %d ticks waiting for"
" BUSY to deassert\n",
- __FUNCTION__, __LINE__, C
FG
_FPGA_WAIT_BUSY);
+ __FUNCTION__, __LINE__, C
ONFIG_SYS
_FPGA_WAIT_BUSY);
(*fn->abort) (cookie);
return FPGA_FAIL;
}
}
#endif
(*fn->abort) (cookie);
return FPGA_FAIL;
}
}
#endif
-#ifdef C
FG
_FPGA_PROG_FEEDBACK
+#ifdef C
ONFIG_SYS
_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.');
#endif
if (bytecount % (bsize / 40) == 0)
putc ('.');
#endif
@@
-349,7
+349,7
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
(*fn->cs) (FALSE, TRUE, cookie);
(*fn->wr) (FALSE, TRUE, cookie);
(*fn->cs) (FALSE, TRUE, cookie);
(*fn->wr) (FALSE, TRUE, cookie);
-#ifdef C
FG
_FPGA_PROG_FEEDBACK
+#ifdef C
ONFIG_SYS
_FPGA_PROG_FEEDBACK
putc ('\n');
#endif
putc ('\n');
#endif
@@
-360,10
+360,10
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
ts = get_timer (0);
ret_val = FPGA_SUCCESS;
while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
ts = get_timer (0);
ret_val = FPGA_SUCCESS;
while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
- if (get_timer (ts) > C
FG
_FPGA_WAIT_CONFIG) {
+ if (get_timer (ts) > C
ONFIG_SYS
_FPGA_WAIT_CONFIG) {
printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
"assert and INIT to deassert\n",
printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
"assert and INIT to deassert\n",
- __FUNCTION__, __LINE__, C
FG
_FPGA_WAIT_CONFIG);
+ __FUNCTION__, __LINE__, C
ONFIG_SYS
_FPGA_WAIT_CONFIG);
(*fn->abort) (cookie);
ret_val = FPGA_FAIL;
break;
(*fn->abort) (cookie);
ret_val = FPGA_FAIL;
break;
@@
-371,7
+371,7
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
}
if (ret_val == FPGA_SUCCESS) {
}
if (ret_val == FPGA_SUCCESS) {
-#ifdef C
FG
_FPGA_PROG_FEEDBACK
+#ifdef C
ONFIG_SYS
_FPGA_PROG_FEEDBACK
printf ("Initialization of FPGA device %d complete\n", cookie);
#endif
/*
printf ("Initialization of FPGA device %d complete\n", cookie);
#endif
/*
@@
-381,7
+381,7
@@
static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize)
(*fn->post) (cookie);
}
} else {
(*fn->post) (cookie);
}
} else {
-#ifdef C
FG
_FPGA_PROG_FEEDBACK
+#ifdef C
ONFIG_SYS
_FPGA_PROG_FEEDBACK
printf ("** Initialization of FPGA device %d FAILED\n",
cookie);
#endif
printf ("** Initialization of FPGA device %d FAILED\n",
cookie);
#endif
@@
-412,7
+412,7
@@
static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
(*fn->clk) (TRUE, TRUE, cookie);
while (bytecount < bsize) {
(*fn->clk) (TRUE, TRUE, cookie);
while (bytecount < bsize) {
-#ifdef C
FG
_FPGA_CHECK_CTRLC
+#ifdef C
ONFIG_SYS
_FPGA_CHECK_CTRLC
if (ctrlc ()) {
(*fn->abort) (cookie);
return FPGA_FAIL;
if (ctrlc ()) {
(*fn->abort) (cookie);
return FPGA_FAIL;
@@
-424,7
+424,7
@@
static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
(*fn->clk) (FALSE, TRUE, cookie);
(*fn->clk) (TRUE, TRUE, cookie);
(*fn->rdata) (&(data[bytecount++]), cookie);
(*fn->clk) (FALSE, TRUE, cookie);
(*fn->clk) (TRUE, TRUE, cookie);
(*fn->rdata) (&(data[bytecount++]), cookie);
-#ifdef C
FG
_FPGA_PROG_FEEDBACK
+#ifdef C
ONFIG_SYS
_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.');
#endif
if (bytecount % (bsize / 40) == 0)
putc ('.');
#endif
@@
-437,7
+437,7
@@
static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize)
(*fn->clk) (FALSE, TRUE, cookie);
(*fn->clk) (TRUE, TRUE, cookie);
(*fn->clk) (FALSE, TRUE, cookie);
(*fn->clk) (TRUE, TRUE, cookie);
-#ifdef C
FG
_FPGA_PROG_FEEDBACK
+#ifdef C
ONFIG_SYS
_FPGA_PROG_FEEDBACK
putc ('\n');
#endif
puts ("Done.\n");
putc ('\n');
#endif
puts ("Done.\n");