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RISCV: configs: tizen_qemu: Enable SBI earlycon
[platform/kernel/linux-starfive.git]
/
certs
/
system_certificates.S
diff --git
a/certs/system_certificates.S
b/certs/system_certificates.S
index
e1645e6
..
003e25d
100644
(file)
--- a/
certs/system_certificates.S
+++ b/
certs/system_certificates.S
@@
-9,10
+9,7
@@
system_certificate_list:
__cert_list_start:
__module_cert_start:
system_certificate_list:
__cert_list_start:
__module_cert_start:
-#if defined(CONFIG_MODULE_SIG) || (defined(CONFIG_IMA_APPRAISE_MODSIG) \
- && defined(CONFIG_MODULES))
.incbin "certs/signing_key.x509"
.incbin "certs/signing_key.x509"
-#endif
__module_cert_end:
.incbin "certs/x509_certificate_list"
__cert_list_end:
__module_cert_end:
.incbin "certs/x509_certificate_list"
__cert_list_end: