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rename CFG_ macros to CONFIG_SYS
[platform/kernel/u-boot.git]
/
board
/
tqc
/
tqm8xx
/
tqm8xx.c
diff --git
a/board/tqc/tqm8xx/tqm8xx.c
b/board/tqc/tqm8xx/tqm8xx.c
index
5537d04
..
9a0f3a0
100644
(file)
--- a/
board/tqc/tqm8xx/tqm8xx.c
+++ b/
board/tqc/tqm8xx/tqm8xx.c
@@
-139,7
+139,7
@@
int checkboard (void)
phys_size_t initdram (int board_type)
{
phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *) C
FG
_IMMR;
+ volatile immap_t *immap = (immap_t *) C
ONFIG_SYS
_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size8, size9, size10;
long int size_b0 = 0;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size8, size9, size10;
long int size_b0 = 0;
@@
-154,7
+154,7
@@
phys_size_t initdram (int board_type)
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
- memctl->memc_mptpr = C
FG
_MPTPR_2BK_8K;
+ memctl->memc_mptpr = C
ONFIG_SYS
_MPTPR_2BK_8K;
/*
* The following value is used as an address (i.e. opcode) for
/*
* The following value is used as an address (i.e. opcode) for
@@
-176,19
+176,19
@@
phys_size_t initdram (int board_type)
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
- memctl->memc_or2 = C
FG
_OR2_PRELIM;
- memctl->memc_br2 = C
FG
_BR2_PRELIM;
+ memctl->memc_or2 = C
ONFIG_SYS
_OR2_PRELIM;
+ memctl->memc_br2 = C
ONFIG_SYS
_BR2_PRELIM;
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
(board_type != 'M') &&
(board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
#ifndef CONFIG_CAN_DRIVER
if ((board_type != 'L') &&
(board_type != 'M') &&
(board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
- memctl->memc_or3 = C
FG
_OR3_PRELIM;
- memctl->memc_br3 = C
FG
_BR3_PRELIM;
+ memctl->memc_or3 = C
ONFIG_SYS
_OR3_PRELIM;
+ memctl->memc_br3 = C
ONFIG_SYS
_BR3_PRELIM;
}
#endif /* CONFIG_CAN_DRIVER */
}
#endif /* CONFIG_CAN_DRIVER */
- memctl->memc_mamr = C
FG_MAMR_8COL & (~(MAMR_PTAE));
/* no refresh yet */
+ memctl->memc_mamr = C
ONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));
/* no refresh yet */
udelay (200);
udelay (200);
@@
-219,7
+219,7
@@
phys_size_t initdram (int board_type)
*
* try 8 column mode
*/
*
* try 8 column mode
*/
- size8 = dram_size (C
FG
_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size8 = dram_size (C
ONFIG_SYS
_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
udelay (1000);
debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
udelay (1000);
@@
-227,30
+227,30
@@
phys_size_t initdram (int board_type)
/*
* try 9 column mode
*/
/*
* try 9 column mode
*/
- size9 = dram_size (C
FG
_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size9 = dram_size (C
ONFIG_SYS
_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
udelay(1000);
debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
udelay(1000);
-#if defined(C
FG
_MAMR_10COL)
+#if defined(C
ONFIG_SYS
_MAMR_10COL)
/*
* try 10 column mode
*/
/*
* try 10 column mode
*/
- size10 = dram_size (C
FG
_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size10 = dram_size (C
ONFIG_SYS
_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
#else
size10 = 0;
debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
#else
size10 = 0;
-#endif /* C
FG
_MAMR_10COL */
+#endif /* C
ONFIG_SYS
_MAMR_10COL */
if ((size8 < size10) && (size9 < size10)) {
size_b0 = size10;
} else if ((size8 < size9) && (size10 < size9)) {
size_b0 = size9;
if ((size8 < size10) && (size9 < size10)) {
size_b0 = size10;
} else if ((size8 < size9) && (size10 < size9)) {
size_b0 = size9;
- memctl->memc_mamr = C
FG
_MAMR_9COL;
+ memctl->memc_mamr = C
ONFIG_SYS
_MAMR_9COL;
udelay (500);
} else {
size_b0 = size8;
udelay (500);
} else {
size_b0 = size8;
- memctl->memc_mamr = C
FG
_MAMR_8COL;
+ memctl->memc_mamr = C
ONFIG_SYS
_MAMR_8COL;
udelay (500);
}
debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
udelay (500);
}
debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
@@
-281,7
+281,7
@@
phys_size_t initdram (int board_type)
*/
if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
/* reduce to 15.6 us (62.4 us / quad) */
*/
if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
/* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = C
FG
_MPTPR_2BK_4K;
+ memctl->memc_mptpr = C
ONFIG_SYS
_MPTPR_2BK_4K;
udelay (1000);
}
udelay (1000);
}
@@
-290,15
+290,15
@@
phys_size_t initdram (int board_type)
*/
if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
*/
if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
- memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | C
FG
_OR_TIMING_SDRAM;
- memctl->memc_br3 = (C
FG
_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+ memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | C
ONFIG_SYS
_OR_TIMING_SDRAM;
+ memctl->memc_br3 = (C
ONFIG_SYS
_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
if (size_b0 > 0) {
/*
* Position Bank 0 immediately above Bank 1
*/
if (size_b0 > 0) {
/*
* Position Bank 0 immediately above Bank 1
*/
- memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | C
FG
_OR_TIMING_SDRAM;
- memctl->memc_br2 = ((C
FG
_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | C
ONFIG_SYS
_OR_TIMING_SDRAM;
+ memctl->memc_br2 = ((C
ONFIG_SYS
_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ size_b1;
} else {
unsigned long reg;
+ size_b1;
} else {
unsigned long reg;
@@
-312,24
+312,24
@@
phys_size_t initdram (int board_type)
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to C
FG
_MPTPR_1BK_8K / _4K */
+ reg >>= 1; /* reduce to C
ONFIG_SYS
_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
}
} else { /* SDRAM Bank 0 is bigger - map first */
memctl->memc_mptpr = reg;
}
} else { /* SDRAM Bank 0 is bigger - map first */
- memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | C
FG
_OR_TIMING_SDRAM;
+ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | C
ONFIG_SYS
_OR_TIMING_SDRAM;
memctl->memc_br2 =
memctl->memc_br2 =
- (C
FG
_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+ (C
ONFIG_SYS
_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
if (size_b1 > 0) {
/*
* Position Bank 1 immediately above Bank 0
*/
memctl->memc_or3 =
if (size_b1 > 0) {
/*
* Position Bank 1 immediately above Bank 0
*/
memctl->memc_or3 =
- ((-size_b1) & 0xFFFF0000) | C
FG
_OR_TIMING_SDRAM;
+ ((-size_b1) & 0xFFFF0000) | C
ONFIG_SYS
_OR_TIMING_SDRAM;
memctl->memc_br3 =
memctl->memc_br3 =
- ((C
FG
_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ ((C
ONFIG_SYS
_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ size_b0;
} else {
unsigned long reg;
+ size_b0;
} else {
unsigned long reg;
@@
-345,7
+345,7
@@
phys_size_t initdram (int board_type)
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to C
FG
_MPTPR_1BK_8K / _4K */
+ reg >>= 1; /* reduce to C
ONFIG_SYS
_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
}
}
memctl->memc_mptpr = reg;
}
}
@@
-356,8
+356,8
@@
phys_size_t initdram (int board_type)
/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
/* Initialize OR3 / BR3 */
/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
/* Initialize OR3 / BR3 */
- memctl->memc_or3 = C
FG
_OR3_CAN;
- memctl->memc_br3 = C
FG
_BR3_CAN;
+ memctl->memc_or3 = C
ONFIG_SYS
_OR3_CAN;
+ memctl->memc_br3 = C
ONFIG_SYS
_BR3_CAN;
/* Initialize MBMR */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
/* Initialize MBMR */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
@@
-397,8
+397,8
@@
phys_size_t initdram (int board_type)
#ifdef CONFIG_ISP1362_USB
/* Initialize OR5 / BR5 */
#ifdef CONFIG_ISP1362_USB
/* Initialize OR5 / BR5 */
- memctl->memc_or5 = C
FG
_OR5_ISP1362;
- memctl->memc_br5 = C
FG
_BR5_ISP1362;
+ memctl->memc_or5 = C
ONFIG_SYS
_OR5_ISP1362;
+ memctl->memc_br5 = C
ONFIG_SYS
_BR5_ISP1362;
#endif /* CONFIG_ISP1362_USB */
return (size_b0 + size_b1);
}
#endif /* CONFIG_ISP1362_USB */
return (size_b0 + size_b1);
}
@@
-415,7
+415,7
@@
phys_size_t initdram (int board_type)
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
- volatile immap_t *immap = (immap_t *) C
FG
_IMMR;
+ volatile immap_t *immap = (immap_t *) C
ONFIG_SYS
_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;
@@
-451,14
+451,14
@@
int board_early_init_r (void)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r (void)
{
#ifdef CONFIG_MISC_INIT_R
int misc_init_r (void)
{
- volatile immap_t *immap = (immap_t *) C
FG
_IMMR;
+ volatile immap_t *immap = (immap_t *) C
ONFIG_SYS
_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile memctl8xx_t *memctl = &immap->im_memctl;
-#ifdef C
FG
_OR_TIMING_FLASH_AT_50MHZ
+#ifdef C
ONFIG_SYS
_OR_TIMING_FLASH_AT_50MHZ
int scy, trlx, flash_or_timing, clk_diff;
int scy, trlx, flash_or_timing, clk_diff;
- scy = (C
FG
_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
- if (C
FG
_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+ scy = (C
ONFIG_SYS
_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+ if (C
ONFIG_SYS
_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
trlx = OR_TRLX;
scy *= 2;
} else {
trlx = OR_TRLX;
scy *= 2;
} else {
@@
-498,29
+498,29
@@
int misc_init_r (void)
scy = 1;
flash_or_timing = (scy << 4) | trlx |
scy = 1;
flash_or_timing = (scy << 4) | trlx |
- (C
FG
_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+ (C
ONFIG_SYS
_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
memctl->memc_or0 =
flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
#else
memctl->memc_or0 =
memctl->memc_or0 =
flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
#else
memctl->memc_or0 =
- C
FG
_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
+ C
ONFIG_SYS
_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
#endif
#endif
- memctl->memc_br0 = (C
FG
_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+ memctl->memc_br0 = (C
ONFIG_SYS
_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
debug ("## BR0: 0x%08x OR0: 0x%08x\n",
memctl->memc_br0, memctl->memc_or0);
if (flash_info[1].size) {
debug ("## BR0: 0x%08x OR0: 0x%08x\n",
memctl->memc_br0, memctl->memc_or0);
if (flash_info[1].size) {
-#ifdef C
FG
_OR_TIMING_FLASH_AT_50MHZ
+#ifdef C
ONFIG_SYS
_OR_TIMING_FLASH_AT_50MHZ
memctl->memc_or1 = flash_or_timing |
(-flash_info[1].size & 0xFFFF8000);
#else
memctl->memc_or1 = flash_or_timing |
(-flash_info[1].size & 0xFFFF8000);
#else
- memctl->memc_or1 = C
FG
_OR_TIMING_FLASH |
+ memctl->memc_or1 = C
ONFIG_SYS
_OR_TIMING_FLASH |
(-flash_info[1].size & 0xFFFF8000);
#endif
memctl->memc_br1 =
(-flash_info[1].size & 0xFFFF8000);
#endif
memctl->memc_br1 =
- ((C
FG
_FLASH_BASE +
+ ((C
ONFIG_SYS
_FLASH_BASE +
flash_info[0].
size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
flash_info[0].
size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
@@
-557,7
+557,7
@@
int misc_init_r (void)
# ifdef CONFIG_IDE_LED
void ide_led (uchar led, uchar status)
{
# ifdef CONFIG_IDE_LED
void ide_led (uchar led, uchar status)
{
- volatile immap_t *immap = (immap_t *) C
FG
_IMMR;
+ volatile immap_t *immap = (immap_t *) C
ONFIG_SYS
_IMMR;
/* We have one led for both pcmcia slots */
if (status) { /* led on */
/* We have one led for both pcmcia slots */
if (status) { /* led on */