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rename CFG_ macros to CONFIG_SYS
[platform/kernel/u-boot.git]
/
board
/
tqc
/
tqm85xx
/
tlb.c
diff --git
a/board/tqc/tqm85xx/tlb.c
b/board/tqc/tqm85xx/tlb.c
index
380448a
..
16b102d
100644
(file)
--- a/
board/tqc/tqm85xx/tlb.c
+++ b/
board/tqc/tqm85xx/tlb.c
@@
-28,19
+28,19
@@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY (0, C
FG_INIT_RAM_ADDR, CFG
_INIT_RAM_ADDR,
+ SET_TLB_ENTRY (0, C
ONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS
_INIT_RAM_ADDR,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY (0, C
FG
_INIT_RAM_ADDR + 4 * 1024,
- C
FG
_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY (0, C
ONFIG_SYS
_INIT_RAM_ADDR + 4 * 1024,
+ C
ONFIG_SYS
_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY (0, C
FG
_INIT_RAM_ADDR + 8 * 1024,
- C
FG
_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY (0, C
ONFIG_SYS
_INIT_RAM_ADDR + 8 * 1024,
+ C
ONFIG_SYS
_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY (0, C
FG
_INIT_RAM_ADDR + 12 * 1024,
- C
FG
_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY (0, C
ONFIG_SYS
_INIT_RAM_ADDR + 12 * 1024,
+ C
ONFIG_SYS
_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@
-50,11
+50,11
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
* 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY (1, C
FG_FLASH_BASE, CFG
_FLASH_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_FLASH_BASE, CONFIG_SYS
_FLASH_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY (1, C
FG
_FLASH_BASE + 0x4000000,
- C
FG
_FLASH_BASE + 0x4000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_FLASH_BASE + 0x4000000,
+ C
ONFIG_SYS
_FLASH_BASE + 0x4000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
@@
-62,7
+62,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY (1, C
FG_PCI1_MEM_PHYS, CFG
_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS
_PCI1_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@
-70,8
+70,8
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY (1, C
FG
_PCI1_MEM_PHYS + 0x10000000,
- C
FG
_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_PCI1_MEM_PHYS + 0x10000000,
+ C
ONFIG_SYS
_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@@
-80,7
+80,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
- SET_TLB_ENTRY (1, C
FG_PCIE1_MEM_BASE, CFG
_PCIE1_MEM_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS
_PCIE1_MEM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@@
-88,8
+88,8
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M PCI express MEM Second half
*/
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M PCI express MEM Second half
*/
- SET_TLB_ENTRY (1, C
FG
_PCIE1_MEM_BASE + 0x10000000,
- C
FG
_PCIE1_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_PCIE1_MEM_BASE + 0x10000000,
+ C
ONFIG_SYS
_PCIE1_MEM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
@@
-97,7
+97,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
- SET_TLB_ENTRY (1, C
FG_RIO_MEM_BASE, CFG
_RIO_MEM_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS
_RIO_MEM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@@
-105,8
+105,8
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
- SET_TLB_ENTRY (1, C
FG
_RIO_MEM_BASE + 0x10000000,
- C
FG
_RIO_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_RIO_MEM_BASE + 0x10000000,
+ C
ONFIG_SYS
_RIO_MEM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#endif /* CONFIG_PCIE */
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#endif /* CONFIG_PCIE */
@@
-117,7
+117,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xe2000000 16M PCI1 IO
* 0xe3000000 16M CAN and NAND Flash
*/
* 0xe2000000 16M PCI1 IO
* 0xe3000000 16M CAN and NAND Flash
*/
- SET_TLB_ENTRY (1, C
FG_CCSRBAR, CFG
_CCSRBAR_PHYS,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_CCSRBAR, CONFIG_SYS
_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
@@
-128,12
+128,12
@@
struct fsl_e_tlb_entry tlb_table[] = {
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
- SET_TLB_ENTRY (1, C
FG_DDR_SDRAM_BASE, CFG
_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS
_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, C
FG
_DDR_SDRAM_BASE + 0x10000000,
- C
FG
_DDR_SDRAM_BASE + 0x10000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_DDR_SDRAM_BASE + 0x10000000,
+ C
ONFIG_SYS
_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
@@
-142,7
+142,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 9: 16M Non-cacheable, guarded
* 0xef000000 16M PCI express IO
*/
* TLB 9: 16M Non-cacheable, guarded
* 0xef000000 16M PCI express IO
*/
- SET_TLB_ENTRY (1, C
FG_PCIE1_IO_BASE, CFG
_PCIE1_IO_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS
_PCIE1_IO_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */
@@
-154,19
+154,19
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xc0000000 1G FLASH
* Out of reset this entry is only 4K.
*/
* 0xc0000000 1G FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY (1, C
FG_FLASH_BASE, CFG
_FLASH_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_FLASH_BASE, CONFIG_SYS
_FLASH_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, C
FG
_FLASH_BASE + 0x10000000,
- C
FG
_FLASH_BASE + 0x10000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_FLASH_BASE + 0x10000000,
+ C
ONFIG_SYS
_FLASH_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, C
FG
_FLASH_BASE + 0x20000000,
- C
FG
_FLASH_BASE + 0x20000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_FLASH_BASE + 0x20000000,
+ C
ONFIG_SYS
_FLASH_BASE + 0x20000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, C
FG
_FLASH_BASE + 0x30000000,
- C
FG
_FLASH_BASE + 0x30000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_FLASH_BASE + 0x30000000,
+ C
ONFIG_SYS
_FLASH_BASE + 0x30000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1),
@@
-174,7
+174,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
* TLB 4: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY (1, C
FG_PCI1_MEM_PHYS, CFG
_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS
_PCI1_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@@
-182,8
+182,8
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 5: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
* TLB 5: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY (1, C
FG
_PCI1_MEM_PHYS + 0x10000000,
- C
FG
_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_PCI1_MEM_PHYS + 0x10000000,
+ C
ONFIG_SYS
_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
@@
-192,7
+192,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 6: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
* TLB 6: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
- SET_TLB_ENTRY (1, C
FG_PCIE1_MEM_BASE, CFG
_PCIE1_MEM_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS
_PCIE1_MEM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
@@
-200,7
+200,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 6: 256M Non-cacheable, guarded
* 0xb0000000 256M Rapid IO MEM First half
*/
* TLB 6: 256M Non-cacheable, guarded
* 0xb0000000 256M Rapid IO MEM First half
*/
- SET_TLB_ENTRY (1, C
FG_RIO_MEM_BASE, CFG
_RIO_MEM_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS
_RIO_MEM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
@@
-212,7
+212,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xa2000000 16M PCI1 IO
* 0xa3000000 16M CAN and NAND Flash
*/
* 0xa2000000 16M PCI1 IO
* 0xa3000000 16M CAN and NAND Flash
*/
- SET_TLB_ENTRY (1, C
FG_CCSRBAR, CFG
_CCSRBAR_PHYS,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_CCSRBAR, CONFIG_SYS
_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_64M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_64M, 1),
@@
-223,12
+223,12
@@
struct fsl_e_tlb_entry tlb_table[] = {
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
- SET_TLB_ENTRY (1, C
FG_DDR_SDRAM_BASE, CFG
_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS
_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY (1, C
FG
_DDR_SDRAM_BASE + 0x10000000,
- C
FG
_DDR_SDRAM_BASE + 0x10000000,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS
_DDR_SDRAM_BASE + 0x10000000,
+ C
ONFIG_SYS
_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_256M, 1),
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_256M, 1),
@@
-237,7
+237,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 10: 16M Non-cacheable, guarded
* 0xaf000000 16M PCI express IO
*/
* TLB 10: 16M Non-cacheable, guarded
* 0xaf000000 16M PCI express IO
*/
- SET_TLB_ENTRY (1, C
FG_PCIE1_IO_BASE, CFG
_PCIE1_IO_BASE,
+ SET_TLB_ENTRY (1, C
ONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS
_PCIE1_IO_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 10, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 10, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */