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SPDX: Convert all of our single license tags to Linux Kernel style
[platform/kernel/u-boot.git]
/
board
/
ti
/
ks2_evm
/
board_k2l.c
diff --git
a/board/ti/ks2_evm/board_k2l.c
b/board/ti/ks2_evm/board_k2l.c
index
70e25f1
..
c28fad5
100644
(file)
--- a/
board/ti/ks2_evm/board_k2l.c
+++ b/
board/ti/ks2_evm/board_k2l.c
@@
-1,10
+1,9
@@
+// SPDX-License-Identifier: GPL-2.0+
/*
* K2L EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
/*
* K2L EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
*/
#include <common.h>
@@
-12,20
+11,38
@@
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
-DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_external_clk(u32 clk)
+{
+ unsigned int clk_freq;
-unsigned int external_clk[ext_clk_count] = {
- [sys_clk] = 122880000,
- [alt_core_clk] = 100000000,
- [pa_clk] = 122880000,
- [tetris_clk] = 122880000,
- [ddr3a_clk] = 100000000,
-};
+ switch (clk) {
+ case sys_clk:
+ clk_freq = 122880000;
+ break;
+ case alt_core_clk:
+ clk_freq = 100000000;
+ break;
+ case pa_clk:
+ clk_freq = 122880000;
+ break;
+ case tetris_clk:
+ clk_freq = 122880000;
+ break;
+ case ddr3a_clk:
+ clk_freq = 100000000;
+ break;
+ default:
+ clk_freq = 0;
+ break;
+ }
+
+ return clk_freq;
+}
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_1000,
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_1000,
- [SPD
800]
= CORE_PLL_1198,
+ [SPD
1200]
= CORE_PLL_1198,
};
s16 divn_val[16] = {
};
s16 divn_val[16] = {
@@
-50,11
+67,11
@@
struct pll_init_data *get_pll_init_data(int pll)
switch (pll) {
case MAIN_PLL:
switch (pll) {
case MAIN_PLL:
- speed = get_max_dev_speed();
+ speed = get_max_dev_speed(
speeds
);
data = &core_pll_config[speed];
break;
case TETRIS_PLL:
data = &core_pll_config[speed];
break;
case TETRIS_PLL:
- speed = get_max_arm_speed();
+ speed = get_max_arm_speed(
speeds
);
data = &tetris_pll_config[speed];
break;
case PASS_PLL:
data = &tetris_pll_config[speed];
break;
case PASS_PLL:
@@
-75,6
+92,7
@@
struct eth_priv_t eth_priv_cfg[] = {
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2L_EMAC1",
},
{
.int_name = "K2L_EMAC1",
@@
-82,6
+100,7
@@
struct eth_priv_t eth_priv_cfg[] = {
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2L_EMAC2",
},
{
.int_name = "K2L_EMAC2",
@@
-89,6
+108,7
@@
struct eth_priv_t eth_priv_cfg[] = {
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2L_EMAC3",
},
{
.int_name = "K2L_EMAC3",
@@
-96,6
+116,7
@@
struct eth_priv_t eth_priv_cfg[] = {
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
};
},
};
@@
-114,6
+135,16
@@
int board_early_init_f(void)
}
#endif
}
#endif
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "keystone-k2l-evm"))
+ return 0;
+
+ return -1;
+}
+#endif
+
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{