+void set_muxconf_regs_essential(void)
+{
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ early_padconf, ARRAY_SIZE(early_padconf));
+}
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
+{
+ struct pad_conf_entry const *pads;
+ struct iodelay_cfg_entry const *iodelay;
+ int npads, niodelays;
+
+ switch (omap_revision()) {
+ case DRA722_ES1_0:
+ pads = core_padconf_array_essential;
+ npads = ARRAY_SIZE(core_padconf_array_essential);
+ iodelay = iodelay_cfg_array;
+ niodelays = ARRAY_SIZE(iodelay_cfg_array);
+ break;
+ case DRA752_ES1_0:
+ case DRA752_ES1_1:
+ pads = dra74x_core_padconf_array;
+ npads = ARRAY_SIZE(dra74x_core_padconf_array);
+ iodelay = dra742_es1_1_iodelay_cfg_array;
+ niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
+ break;
+ default:
+ case DRA752_ES2_0:
+ pads = dra74x_core_padconf_array;
+ npads = ARRAY_SIZE(dra74x_core_padconf_array);
+ iodelay = dra742_es2_0_iodelay_cfg_array;
+ niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
+ /* Setup port1 and port2 for rgmii with 'no-id' mode */
+ clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
+ RGMII1_ID_MODE_N_MASK);
+ break;
+ }
+ __recalibrate_iodelay(pads, npads, iodelay, niodelays);
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)