+#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
+static void nand_pinmux_setup(void)
+{
+ unsigned int pin;
+
+ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+
+#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
+ for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+#endif
+ /* sun4i / sun7i do have a PC23, but it is not used for nand,
+ * only sun7i has a PC24 */
+#ifdef CONFIG_MACH_SUN7I
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
+#endif
+}
+
+static void nand_clock_setup(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
+#ifdef CONFIG_MACH_SUN9I
+ setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
+#else
+ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
+#endif
+ setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
+}
+
+void board_nand_init(void)
+{
+ nand_pinmux_setup();
+ nand_clock_setup();
+}
+#endif
+