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rename CFG_ macros to CONFIG_SYS
[platform/kernel/u-boot.git]
/
board
/
socrates
/
tlb.c
diff --git
a/board/socrates/tlb.c
b/board/socrates/tlb.c
index
d255cea
..
b91b1ea
100644
(file)
--- a/
board/socrates/tlb.c
+++ b/
board/socrates/tlb.c
@@
-31,16
+31,16
@@
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR, CFG
_INIT_RAM_ADDR,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS
_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR + 4 * 1024 , CFG
_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS
_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR + 8 * 1024 , CFG
_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS
_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, C
FG_INIT_RAM_ADDR + 12 * 1024 , CFG
_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0, C
ONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS
_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
@@
-50,7
+50,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xfc000000 64M FLASH
* Out of reset this entry is only 4K.
*/
* 0xfc000000 64M FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, C
FG_FLASH_BASE, CFG
_FLASH_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_FLASH_BASE, CONFIG_SYS
_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
@@
-58,7
+58,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
- SET_TLB_ENTRY(1, C
FG_PCI1_MEM_PHYS, CFG
_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS
_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@@
-66,16
+66,16
@@
struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
- SET_TLB_ENTRY(1, C
FG_PCI1_MEM_PHYS + 0x10000000, CFG
_PCI1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS
_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
-#if defined(C
FG
_FPGA_BASE)
+#if defined(C
ONFIG_SYS
_FPGA_BASE)
/*
* TLB 4: 1M Non-cacheable, guarded
* 0xc0000000 1M FPGA and NAND
*/
/*
* TLB 4: 1M Non-cacheable, guarded
* 0xc0000000 1M FPGA and NAND
*/
- SET_TLB_ENTRY(1, C
FG_FPGA_BASE, CFG
_FPGA_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_FPGA_BASE, CONFIG_SYS
_FPGA_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_1M, 1),
#endif
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_1M, 1),
#endif
@@
-87,7
+87,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* (0xcbfc0000 256K LIME GDC MMIO)
* MMIO is relocatable and could be at 0xcbfc0000
*/
* (0xcbfc0000 256K LIME GDC MMIO)
* MMIO is relocatable and could be at 0xcbfc0000
*/
- SET_TLB_ENTRY(1, C
FG_LIME_BASE, CFG
_LIME_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_LIME_BASE, CONFIG_SYS
_LIME_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64M, 1),
@@
-96,7
+96,7
@@
struct fsl_e_tlb_entry tlb_table[] = {
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
- SET_TLB_ENTRY(1, C
FG_CCSRBAR, CFG
_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_CCSRBAR, CONFIG_SYS
_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
@@
-107,11
+107,11
@@
struct fsl_e_tlb_entry tlb_table[] = {
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
- SET_TLB_ENTRY(1, C
FG_DDR_SDRAM_BASE, CFG
_DDR_SDRAM_BASE,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS
_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, C
FG_DDR_SDRAM_BASE + 0x10000000, CFG
_DDR_SDRAM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, C
ONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS
_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
};
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
};