- mtebc (pb4ap, 0x01805940);
- mtebc (pb4cr, 0x7401a000);
- mtebc (pb5ap, 0x01805940);
- mtebc (pb5cr, 0x7401a000);
- mtebc (pb6ap, 0x0);
- mtebc (pb6cr, 0x0);
- mtebc (pb7ap, 0x0);
- mtebc (pb7cr, 0x0);
+ mtebc (PB4AP, 0x01805940);
+ mtebc (PB4CR, 0x7401a000);
+ mtebc (PB5AP, 0x01805940);
+ mtebc (PB5CR, 0x7401a000);
+ mtebc (PB6AP, 0x0);
+ mtebc (PB6CR, 0x0);
+ mtebc (PB7AP, 0x0);
+ mtebc (PB7CR, 0x0);
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
/* setup other implementation specific details */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
/* setup other implementation specific details */
/* Setup the GPIOs */
writel (0x08008000, 0xEF600700); /* Output states */
writel (0x00000000, 0xEF600718); /* Open Drain control */
writel (0x68098000, 0xEF600704); /* Output control */
} else {
/* Setup the GPIOs */
writel (0x08008000, 0xEF600700); /* Output states */
writel (0x00000000, 0xEF600718); /* Open Drain control */
writel (0x68098000, 0xEF600704); /* Output control */
} else {
/* Setup the GPIOs */
writel (0x08000000, 0xEF600700); /* Output states */
writel (0x14000000, 0xEF600718); /* Open Drain control */
/* Setup the GPIOs */
writel (0x08000000, 0xEF600700); /* Output states */
writel (0x14000000, 0xEF600718); /* Open Drain control */
/* CPC0_ER: enable sleep mode of (currently) unused components */
/* CPC0_FR: force unused components into sleep mode */
/* CPC0_ER: enable sleep mode of (currently) unused components */
/* CPC0_FR: force unused components into sleep mode */
- mtdcr (cpmer, 0x3F800000);
- mtdcr (cpmfr, 0x14000000);
+ mtdcr (CPMER, 0x3F800000);
+ mtdcr (CPMFR, 0x14000000);
-static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap,
- pb5ap, pb6ap, pb7ap};
-static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr,
- pb5cr, pb6cr, pb7cr};
+static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP,
+ PB5AP, PB6AP, PB7AP};
+static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR,
+ PB5CR, PB6CR, PB7CR};
- mtdcr (ebccfga, ap[nr]);
- ul1 = mfdcr (ebccfgd);
- mtdcr (ebccfga, cr[nr]);
- ul2 = mfdcr(ebccfgd);
+ mtdcr (EBC0_CFGADDR, ap[nr]);
+ ul1 = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, cr[nr]);
+ ul2 = mfdcr(EBC0_CFGDATA);
if (!(ul1 & 0x80000000)) {
puts(" Controller disabled\n");
return 0;
}
for (i = 0; i < 4; i++) {
if (!(ul1 & 0x80000000)) {
puts(" Controller disabled\n");
return 0;
}
for (i = 0; i < 4; i++) {
printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
puts ("Misc:\n");
printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
puts ("Misc:\n");
mems += printSDRAMConfig (3, ul1);
return (mems * 1024 * 1024);
mems += printSDRAMConfig (3, ul1);
return (mems * 1024 * 1024);