projects
/
platform
/
kernel
/
u-boot.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
rename CFG_ macros to CONFIG_SYS
[platform/kernel/u-boot.git]
/
board
/
sbc8548
/
sbc8548.c
diff --git
a/board/sbc8548/sbc8548.c
b/board/sbc8548/sbc8548.c
index
f31d7d6
..
21f82f2
100644
(file)
--- a/
board/sbc8548/sbc8548.c
+++ b/
board/sbc8548/sbc8548.c
@@
-53,9
+53,9
@@
int board_early_init_f (void)
int checkboard (void)
{
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(C
FG
_MPC85xx_GUTS_ADDR);
- volatile ccsr_local_ecm_t *ecm = (void *)(C
FG
_MPC85xx_ECM_ADDR);
- volatile u_char *rev= (void *)C
FG
_BD_REV;
+ volatile ccsr_gur_t *gur = (void *)(C
ONFIG_SYS
_MPC85xx_GUTS_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(C
ONFIG_SYS
_MPC85xx_ECM_ADDR);
+ volatile u_char *rev= (void *)C
ONFIG_SYS
_BD_REV;
printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
(*rev) >> 4);
printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
(*rev) >> 4);
@@
-98,7
+98,7
@@
initdram(int board_type)
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
- volatile ccsr_gur_t *gur = (void *)(C
FG
_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(C
ONFIG_SYS
_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
@@
-135,8
+135,8
@@
initdram(int board_type)
void
local_bus_init(void)
{
void
local_bus_init(void)
{
- volatile ccsr_gur_t *gur = (void *)(C
FG
_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(C
FG
_MPC85xx_LBC_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(C
ONFIG_SYS
_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(C
ONFIG_SYS
_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
uint clkdiv;
uint lbc_hz;
@@
-169,44
+169,44
@@
local_bus_init(void)
void
sdram_init(void)
{
void
sdram_init(void)
{
-#if defined(C
FG_OR3_PRELIM) && defined(CFG
_BR3_PRELIM)
+#if defined(C
ONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS
_BR3_PRELIM)
uint idx;
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(C
FG
_MPC85xx_LBC_ADDR);
- uint *sdram_addr = (uint *)C
FG
_LBC_SDRAM_BASE;
+ volatile ccsr_lbc_t *lbc = (void *)(C
ONFIG_SYS
_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)C
ONFIG_SYS
_LBC_SDRAM_BASE;
uint lsdmr_common;
puts(" SDRAM: ");
uint lsdmr_common;
puts(" SDRAM: ");
- print_size (C
FG
_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+ print_size (C
ONFIG_SYS
_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers
*/
/*
* Setup SDRAM Base and Option Registers
*/
- lbc->or3 = C
FG
_OR3_PRELIM;
+ lbc->or3 = C
ONFIG_SYS
_OR3_PRELIM;
asm("msync");
asm("msync");
- lbc->br3 = C
FG
_BR3_PRELIM;
+ lbc->br3 = C
ONFIG_SYS
_BR3_PRELIM;
asm("msync");
asm("msync");
- lbc->lbcr = C
FG
_LBC_LBCR;
+ lbc->lbcr = C
ONFIG_SYS
_LBC_LBCR;
asm("msync");
asm("msync");
- lbc->lsrt = C
FG
_LBC_LSRT;
- lbc->mrtpr = C
FG
_LBC_MRTPR;
+ lbc->lsrt = C
ONFIG_SYS
_LBC_LSRT;
+ lbc->mrtpr = C
ONFIG_SYS
_LBC_MRTPR;
asm("msync");
/*
* MPC8548 uses "new" 15-16 style addressing.
*/
asm("msync");
/*
* MPC8548 uses "new" 15-16 style addressing.
*/
- lsdmr_common = C
FG
_LBC_LSDMR_COMMON;
- lsdmr_common |= C
FG
_LBC_LSDMR_BSMA1516;
+ lsdmr_common = C
ONFIG_SYS
_LBC_LSDMR_COMMON;
+ lsdmr_common |= C
ONFIG_SYS
_LBC_LSDMR_BSMA1516;
/*
* Issue PRECHARGE ALL command.
*/
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | C
FG
_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | C
ONFIG_SYS
_LBC_LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@
-216,7
+216,7
@@
sdram_init(void)
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | C
FG
_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | C
ONFIG_SYS
_LBC_LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@
-226,7
+226,7
@@
sdram_init(void)
/*
* Issue 8 MODE-set command.
*/
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | C
FG
_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | C
ONFIG_SYS
_LBC_LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@
-235,7
+235,7
@@
sdram_init(void)
/*
* Issue NORMAL OP command.
*/
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | C
FG
_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | C
ONFIG_SYS
_LBC_LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@
-244,17
+244,17
@@
sdram_init(void)
#endif /* enable SDRAM init */
}
#endif /* enable SDRAM init */
}
-#if defined(C
FG
_DRAM_TEST)
+#if defined(C
ONFIG_SYS
_DRAM_TEST)
int
testdram(void)
{
int
testdram(void)
{
- uint *pstart = (uint *) C
FG
_MEMTEST_START;
- uint *pend = (uint *) C
FG
_MEMTEST_END;
+ uint *pstart = (uint *) C
ONFIG_SYS
_MEMTEST_START;
+ uint *pend = (uint *) C
ONFIG_SYS
_MEMTEST_END;
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
- C
FG
_MEMTEST_START,
- C
FG
_MEMTEST_END);
+ C
ONFIG_SYS
_MEMTEST_START,
+ C
ONFIG_SYS
_MEMTEST_END);
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
@@
-290,9
+290,9
@@
testdram(void)
************************************************************************/
long int fixed_sdram (void)
{
************************************************************************/
long int fixed_sdram (void)
{
- #define C
FG
_DDR_CONTROL 0xc300c000
+ #define C
ONFIG_SYS
_DDR_CONTROL 0xc300c000
- volatile ccsr_ddr_t *ddr = (void *)(C
FG
_MPC85xx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr = (void *)(C
ONFIG_SYS
_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = 0x0000007f;
ddr->cs1_bnds = 0x008000ff;
ddr->cs0_bnds = 0x0000007f;
ddr->cs1_bnds = 0x008000ff;
@@
-319,12
+319,12
@@
long int fixed_sdram (void)
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
- ddr->sdram_cfg = (C
FG
_DDR_CONTROL | 0x20000000);
+ ddr->sdram_cfg = (C
ONFIG_SYS
_DDR_CONTROL | 0x20000000);
#else
#else
- ddr->sdram_cfg = C
FG
_DDR_CONTROL;
+ ddr->sdram_cfg = C
ONFIG_SYS
_DDR_CONTROL;
#endif
#endif
- return C
FG
_SDRAM_SIZE * 1024 * 1024;
+ return C
ONFIG_SYS
_SDRAM_SIZE * 1024 * 1024;
}
#endif
}
#endif
@@
-367,11
+367,11
@@
int first_free_busno=0;
void
pci_init_board(void)
{
void
pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(C
FG
_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(C
ONFIG_SYS
_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_PCI1
{
#ifdef CONFIG_PCI1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) C
FG
_PCI1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) C
ONFIG_SYS
_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
struct pci_config_table *table;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
struct pci_config_table *table;
@@
-397,24
+397,24
@@
pci_init_board(void)
/* inbound */
pci_set_region(hose->regions + 0,
/* inbound */
pci_set_region(hose->regions + 0,
- C
FG
_PCI_MEMORY_BUS,
- C
FG
_PCI_MEMORY_PHYS,
- C
FG
_PCI_MEMORY_SIZE,
+ C
ONFIG_SYS
_PCI_MEMORY_BUS,
+ C
ONFIG_SYS
_PCI_MEMORY_PHYS,
+ C
ONFIG_SYS
_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- C
FG
_PCI1_MEM_BASE,
- C
FG
_PCI1_MEM_PHYS,
- C
FG
_PCI1_MEM_SIZE,
+ C
ONFIG_SYS
_PCI1_MEM_BASE,
+ C
ONFIG_SYS
_PCI1_MEM_PHYS,
+ C
ONFIG_SYS
_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- C
FG
_PCI1_IO_BASE,
- C
FG
_PCI1_IO_PHYS,
- C
FG
_PCI1_IO_SIZE,
+ C
ONFIG_SYS
_PCI1_IO_BASE,
+ C
ONFIG_SYS
_PCI1_IO_PHYS,
+ C
ONFIG_SYS
_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
PCI_REGION_IO);
hose->region_count = 3;
@@
-466,7
+466,7
@@
pci_init_board(void)
#ifdef CONFIG_PCIE1
{
#ifdef CONFIG_PCIE1
{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) C
FG
_PCIE1_ADDR;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) C
ONFIG_SYS
_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
@@
-486,23
+486,23
@@
pci_init_board(void)
/* inbound */
pci_set_region(hose->regions + 0,
/* inbound */
pci_set_region(hose->regions + 0,
- C
FG
_PCI_MEMORY_BUS,
- C
FG
_PCI_MEMORY_PHYS,
- C
FG
_PCI_MEMORY_SIZE,
+ C
ONFIG_SYS
_PCI_MEMORY_BUS,
+ C
ONFIG_SYS
_PCI_MEMORY_PHYS,
+ C
ONFIG_SYS
_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region(hose->regions + 1,
- C
FG
_PCIE1_MEM_BASE,
- C
FG
_PCIE1_MEM_PHYS,
- C
FG
_PCIE1_MEM_SIZE,
+ C
ONFIG_SYS
_PCIE1_MEM_BASE,
+ C
ONFIG_SYS
_PCIE1_MEM_PHYS,
+ C
ONFIG_SYS
_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
- C
FG
_PCIE1_IO_BASE,
- C
FG
_PCIE1_IO_PHYS,
- C
FG
_PCIE1_IO_SIZE,
+ C
ONFIG_SYS
_PCIE1_IO_BASE,
+ C
ONFIG_SYS
_PCIE1_IO_PHYS,
+ C
ONFIG_SYS
_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
PCI_REGION_IO);
hose->region_count = 3;