* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
* | +----------- Operating Mode = Standard
* +-------------- Write Burst Mode = Programmed Burst Length
*/
* | +----------- Operating Mode = Standard
* +-------------- Write Burst Mode = Programmed Burst Length
*/
/*
* Map controller banks 1 to the SDRAM banks 1 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
/*
* Map controller banks 1 to the SDRAM banks 1 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/