- debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
-#ifdef CONFIG_PCIE1
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
- if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
- SET_STD_PCIE_INFO(pci_info[num], 1);
- pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "End Point" : "Root Complex",
- pci_info[num].regs);
-
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
- } else {
- printf (" PCIE1: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
-
- if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
- SET_STD_PCIE_INFO(pci_info[num], 2);
- pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
- pcie_ep ? "End Point" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
- } else {
- printf (" PCIE2: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
-#endif